From f20222a83c8f76c52c89201627857c055e879f02 Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Mon, 5 Mar 2018 13:27:26 +0000 Subject: [PATCH] [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers These instructions require that the two S registers are adjacent (but not the R registers), because only the first register is included in the encoding, but we were not checking this in the assembler. Differential revision: https://reviews.llvm.org/D44084 llvm-svn: 326696 --- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 18 ++++++++++++++++++ llvm/test/MC/ARM/vmov-pair-diags.s | 6 ++++++ 2 files changed, 24 insertions(+) create mode 100644 llvm/test/MC/ARM/vmov-pair-diags.s diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 597d654bed93..cbbbdc035e88 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -6631,6 +6631,24 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, "code specified"); break; } + case ARM::VMOVRRS: { + // Source registers must be sequential. + const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); + const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg()); + if (Sm1 != Sm + 1) + return Error(Operands[5]->getStartLoc(), + "source operands must be sequential"); + break; + } + case ARM::VMOVSRR: { + // Destination registers must be sequential. + const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); + const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + if (Sm1 != Sm + 1) + return Error(Operands[3]->getStartLoc(), + "destination operands must be sequential"); + break; + } } return false; diff --git a/llvm/test/MC/ARM/vmov-pair-diags.s b/llvm/test/MC/ARM/vmov-pair-diags.s new file mode 100644 index 000000000000..561eca6c2787 --- /dev/null +++ b/llvm/test/MC/ARM/vmov-pair-diags.s @@ -0,0 +1,6 @@ +@ RUN: not llvm-mc -triple armv7-eabi < %s 2>&1 | FileCheck %s + +vmov r0, r1, s0, s2 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operands must be sequential +vmov s0, s2, r0, r1 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: destination operands must be sequential