forked from OSchip/llvm-project
Revert rL292621. Caused some internal build bot failures in apple.
llvm-svn: 292984
This commit is contained in:
Wei Mi
parent
3943d2b0d7
commit
f1cf0278e8
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@ -22,7 +22,6 @@
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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@ -190,9 +189,6 @@ namespace {
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/// This returns true if an interval was modified.
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bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
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/// We found a copy which can be moved to its less frequent predecessor.
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bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
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/// If the source of a copy is defined by a
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/// trivial computation, replace the copy by rematerialize the definition.
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bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
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@ -865,167 +861,6 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
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return true;
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}
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/// For copy B = A in BB2, if A is defined by A = B in BB0 which is a
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/// predecessor of BB2, and if B is not redefined on the way from A = B
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/// in BB2 to B = A in BB2, B = A in BB2 is partially redundant if the
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/// execution goes through the path from BB0 to BB2. We may move B = A
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/// to the predecessor without such reversed copy.
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/// So we will transform the program from:
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/// BB0:
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/// A = B; BB1:
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/// ... ...
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/// / \ /
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/// BB2:
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/// ...
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/// B = A;
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///
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/// to:
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///
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/// BB0: BB1:
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/// A = B; ...
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/// ... B = A;
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/// / \ /
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/// BB2:
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/// ...
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///
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/// A special case is when BB0 and BB2 are the same BB which is the only
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/// BB in a loop:
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/// BB1:
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/// ...
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/// BB0/BB2: ----
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/// B = A; |
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/// ... |
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/// A = B; |
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/// |-------
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/// |
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/// We may hoist B = A from BB0/BB2 to BB1.
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///
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/// The major preconditions for correctness to remove such partial
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/// redundancy include:
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/// 1. A in B = A in BB2 is defined by a PHI in BB2, and one operand of
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/// the PHI is defined by the reversed copy A = B in BB0.
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/// 2. No B is referenced from the start of BB2 to B = A.
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/// 3. No B is defined from A = B to the end of BB0.
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/// 4. BB1 has only one successor.
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///
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/// 2 and 4 implicitly ensure B is not live at the end of BB1.
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/// 4 guarantees BB2 is hotter than BB1, so we can only move a copy to a
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/// colder place, which not only prevent endless loop, but also make sure
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/// the movement of copy is beneficial.
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bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
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MachineInstr &CopyMI) {
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assert(!CP.isPhys());
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if (!CopyMI.isFullCopy())
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return false;
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MachineBasicBlock &MBB = *CopyMI.getParent();
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if (MBB.isEHPad())
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return false;
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if (MBB.pred_size() != 2)
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return false;
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LiveInterval &IntA =
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LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
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LiveInterval &IntB =
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LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
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// A is defined by PHI at the entry of MBB.
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SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
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VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx);
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assert(AValNo && !AValNo->isUnused() && "COPY source not live");
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if (!AValNo->isPHIDef())
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return false;
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// No B is referenced before CopyMI in MBB.
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if (IntB.overlaps(LIS->getMBBStartIdx(&MBB), CopyIdx))
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return false;
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// MBB has two predecessors: one contains A = B so no copy will be inserted
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// for it. The other one will have a copy moved from MBB.
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bool FoundReverseCopy = false;
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MachineBasicBlock *CopyLeftBB = nullptr;
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for (MachineBasicBlock *Pred : MBB.predecessors()) {
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VNInfo *PVal = IntA.getVNInfoBefore(LIS->getMBBEndIdx(Pred));
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MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
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if (!DefMI || !DefMI->isFullCopy()) {
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CopyLeftBB = Pred;
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continue;
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}
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// Check DefMI is a reverse copy and it is in BB Pred.
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if (DefMI->getOperand(0).getReg() != IntA.reg ||
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DefMI->getOperand(1).getReg() != IntB.reg ||
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DefMI->getParent() != Pred) {
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CopyLeftBB = Pred;
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continue;
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}
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// If there is any other def of B after DefMI and before the end of Pred,
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// we need to keep the copy of B = A at the end of Pred if we remove
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// B = A from MBB.
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bool ValB_Changed = false;
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for (auto VNI : IntB.valnos) {
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if (VNI->isUnused())
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continue;
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if (PVal->def < VNI->def && VNI->def < LIS->getMBBEndIdx(Pred)) {
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ValB_Changed = true;
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break;
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}
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}
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if (ValB_Changed) {
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CopyLeftBB = Pred;
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continue;
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}
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FoundReverseCopy = true;
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}
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// If no reverse copy is found in predecessors, nothing to do.
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if (!FoundReverseCopy)
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return false;
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// If CopyLeftBB is nullptr, it means every predecessor of MBB contains
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// reverse copy, CopyMI can be removed trivially if only IntA/IntB is updated.
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// If CopyLeftBB is not nullptr, move CopyMI from MBB to CopyLeftBB and
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// update IntA/IntB.
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//
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// If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
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// MBB is hotter than CopyLeftBB.
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if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
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return false;
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// Now ok to move copy.
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if (CopyLeftBB) {
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DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to BB#"
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<< CopyLeftBB->getNumber() << '\t' << CopyMI);
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// Insert new copy to CopyLeftBB.
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auto InsPos = CopyLeftBB->getFirstTerminator();
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MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
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TII->get(TargetOpcode::COPY), IntB.reg)
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.addReg(IntA.reg);
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SlotIndex NewCopyIdx =
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LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
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VNInfo *VNI = IntB.getNextValue(NewCopyIdx, LIS->getVNInfoAllocator());
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IntB.createDeadDef(VNI);
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} else {
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DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from BB#"
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<< MBB.getNumber() << '\t' << CopyMI);
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}
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// Remove CopyMI.
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SmallVector<SlotIndex, 8> EndPoints;
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VNInfo *BValNo = IntB.Query(CopyIdx.getRegSlot()).valueOutOrDead();
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LIS->pruneValue(IntB, CopyIdx.getRegSlot(), &EndPoints);
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BValNo->markUnused();
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LIS->RemoveMachineInstrFromMaps(CopyMI);
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CopyMI.eraseFromParent();
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// Extend IntB to the EndPoints of its original live interval.
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LIS->extendToIndices(IntB, EndPoints);
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shrinkToUses(&IntA);
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return true;
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}
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/// Returns true if @p MI defines the full vreg @p Reg, as opposed to just
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/// defining a subregister.
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static bool definesFullReg(const MachineInstr &MI, unsigned Reg) {
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@ -1651,12 +1486,6 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
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}
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}
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// Try and see if we can partially eliminate the copy by moving the copy to
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// its predecessor.
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if (!CP.isPartial() && !CP.isPhys())
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if (removePartialRedundancy(CP, *CopyMI))
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return true;
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// Otherwise, we are unable to join the intervals.
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DEBUG(dbgs() << "\tInterference!\n");
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Again = true; // May be possible to coalesce later.
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@ -1,281 +0,0 @@
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; RUN: llc -regalloc=greedy -verify-coalescing -mtriple=x86_64-unknown-linux-gnu < %s
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; Check the live range is updated properly after register coalescing.
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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@.str = internal unnamed_addr constant { [17 x i8], [47 x i8] } { [17 x i8] c"0123456789ABCDEF\00", [47 x i8] zeroinitializer }, align 32
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@b = common local_unnamed_addr global i32 0, align 4
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@a = common local_unnamed_addr global i32* null, align 8
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@__sancov_gen_cov = private global [9 x i32] zeroinitializer
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; Function Attrs: nounwind sanitize_address
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define void @fn2(i8* %p1) local_unnamed_addr #0 {
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entry:
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%0 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 4) to i32*) monotonic, align 4
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%1 = icmp sge i32 0, %0
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br i1 %1, label %2, label %3
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; <label>:2: ; preds = %entry
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call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 4) to i32*))
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call void asm sideeffect "", ""()
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br label %3
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; <label>:3: ; preds = %entry, %2
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br label %while.cond.outer
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while.cond.outer: ; preds = %75, %3
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%e.0.ph = phi i8* [ %e.058, %75 ], [ undef, %3 ]
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%c.0.ph = phi i32* [ %c.059, %75 ], [ undef, %3 ]
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%p1.addr.0.ph = phi i8* [ %incdec.ptr60, %75 ], [ %p1, %3 ]
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%4 = ptrtoint i8* %p1.addr.0.ph to i64
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%5 = lshr i64 %4, 3
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%6 = add i64 %5, 2147450880
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%7 = inttoptr i64 %6 to i8*
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%8 = load i8, i8* %7
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%9 = icmp ne i8 %8, 0
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br i1 %9, label %10, label %15
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; <label>:10: ; preds = %while.cond.outer
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%11 = and i64 %4, 7
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%12 = trunc i64 %11 to i8
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%13 = icmp sge i8 %12, %8
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br i1 %13, label %14, label %15
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; <label>:14: ; preds = %10
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call void @__asan_report_load1(i64 %4)
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call void asm sideeffect "", ""()
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unreachable
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; <label>:15: ; preds = %10, %while.cond.outer
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%16 = load i8, i8* %p1.addr.0.ph, align 1
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call void @__sanitizer_cov_trace_cmp1(i8 %16, i8 0)
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%cmp57 = icmp eq i8 %16, 0
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br i1 %cmp57, label %while.cond.outer.enoent.loopexit96_crit_edge, label %while.body.preheader
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while.cond.outer.enoent.loopexit96_crit_edge: ; preds = %15
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%17 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 8) to i32*) monotonic, align 4
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%18 = icmp sge i32 0, %17
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br i1 %18, label %19, label %20
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; <label>:19: ; preds = %while.cond.outer.enoent.loopexit96_crit_edge
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call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 8) to i32*))
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call void asm sideeffect "", ""()
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br label %20
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; <label>:20: ; preds = %while.cond.outer.enoent.loopexit96_crit_edge, %19
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br label %enoent.loopexit96
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while.body.preheader: ; preds = %15
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br label %while.body
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while.body: ; preds = %56, %while.body.preheader
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%21 = phi i8 [ %52, %56 ], [ %16, %while.body.preheader ]
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%p1.addr.0.ph.pn = phi i8* [ %incdec.ptr60, %56 ], [ %p1.addr.0.ph, %while.body.preheader ]
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%c.059 = phi i32* [ %incdec.ptr18, %56 ], [ %c.0.ph, %while.body.preheader ]
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%e.058 = phi i8* [ %incdec.ptr60, %56 ], [ %e.0.ph, %while.body.preheader ]
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%incdec.ptr60 = getelementptr inbounds i8, i8* %p1.addr.0.ph.pn, i64 1
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%conv = sext i8 %21 to i32
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%call = tail call i32 (i8*, i32, ...) bitcast (i32 (...)* @fn3 to i32 (i8*, i32, ...)*)(i8* getelementptr inbounds ({ [17 x i8], [47 x i8] }, { [17 x i8], [47 x i8] }* @.str, i32 0, i32 0, i64 0), i32 %conv) #2
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call void @__sanitizer_cov_trace_cmp4(i32 %call, i32 0)
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%tobool = icmp eq i32 %call, 0
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br i1 %tobool, label %if.end5, label %cleanup
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if.end5: ; preds = %while.body
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call void @__sanitizer_cov_trace_cmp1(i8 %21, i8 58)
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%cmp6 = icmp eq i8 %21, 58
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br i1 %cmp6, label %if.end14, label %cleanup.thread40
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if.end14: ; preds = %if.end5
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%22 = load i8, i8* inttoptr (i64 add (i64 lshr (i64 ptrtoint (i32** @a to i64), i64 3), i64 2147450880) to i8*)
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%23 = icmp ne i8 %22, 0
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br i1 %23, label %24, label %25
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; <label>:24: ; preds = %if.end14
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call void @__asan_report_load8(i64 ptrtoint (i32** @a to i64))
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call void asm sideeffect "", ""()
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unreachable
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; <label>:25: ; preds = %if.end14
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%26 = load i32*, i32** @a, align 8
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%tobool15 = icmp eq i32* %26, null
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br i1 %tobool15, label %cleanup.thread39, label %cleanup23.loopexit
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cleanup.thread39: ; preds = %25
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%incdec.ptr18 = getelementptr inbounds i32, i32* %c.059, i64 1
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%27 = ptrtoint i32* %c.059 to i64
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%28 = lshr i64 %27, 3
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%29 = add i64 %28, 2147450880
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%30 = inttoptr i64 %29 to i8*
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%31 = load i8, i8* %30
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%32 = icmp ne i8 %31, 0
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br i1 %32, label %33, label %39
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; <label>:33: ; preds = %cleanup.thread39
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%34 = and i64 %27, 7
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%35 = add i64 %34, 3
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%36 = trunc i64 %35 to i8
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%37 = icmp sge i8 %36, %31
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br i1 %37, label %38, label %39
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; <label>:38: ; preds = %33
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call void @__asan_report_store4(i64 %27)
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call void asm sideeffect "", ""()
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unreachable
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; <label>:39: ; preds = %33, %cleanup.thread39
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store i32 0, i32* %c.059, align 4
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%40 = ptrtoint i8* %incdec.ptr60 to i64
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%41 = lshr i64 %40, 3
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%42 = add i64 %41, 2147450880
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%43 = inttoptr i64 %42 to i8*
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%44 = load i8, i8* %43
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%45 = icmp ne i8 %44, 0
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br i1 %45, label %46, label %51
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; <label>:46: ; preds = %39
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%47 = and i64 %40, 7
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%48 = trunc i64 %47 to i8
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%49 = icmp sge i8 %48, %44
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br i1 %49, label %50, label %51
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; <label>:50: ; preds = %46
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call void @__asan_report_load1(i64 %40)
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call void asm sideeffect "", ""()
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unreachable
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; <label>:51: ; preds = %46, %39
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%52 = load i8, i8* %incdec.ptr60, align 1
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call void @__sanitizer_cov_trace_cmp1(i8 %52, i8 0)
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%cmp = icmp eq i8 %52, 0
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br i1 %cmp, label %enoent.loopexit, label %cleanup.thread39.while.body_crit_edge
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cleanup.thread39.while.body_crit_edge: ; preds = %51
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%53 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 12) to i32*) monotonic, align 4
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%54 = icmp sge i32 0, %53
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br i1 %54, label %55, label %56
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; <label>:55: ; preds = %cleanup.thread39.while.body_crit_edge
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call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 12) to i32*))
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call void asm sideeffect "", ""()
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br label %56
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; <label>:56: ; preds = %cleanup.thread39.while.body_crit_edge, %55
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br label %while.body
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cleanup.thread40: ; preds = %if.end5
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%57 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 16) to i32*) monotonic, align 4
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%58 = icmp sge i32 0, %57
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br i1 %58, label %59, label %60
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; <label>:59: ; preds = %cleanup.thread40
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call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 16) to i32*))
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call void asm sideeffect "", ""()
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br label %60
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; <label>:60: ; preds = %cleanup.thread40, %59
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%call20 = tail call i32 (i8*, ...) bitcast (i32 (...)* @fn4 to i32 (i8*, ...)*)(i8* %e.058) #2
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br label %enoent
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|
||||
cleanup: ; preds = %while.body
|
||||
%61 = load i8, i8* inttoptr (i64 add (i64 lshr (i64 ptrtoint (i32* @b to i64), i64 3), i64 2147450880) to i8*)
|
||||
%62 = icmp ne i8 %61, 0
|
||||
br i1 %62, label %63, label %66
|
||||
|
||||
; <label>:63: ; preds = %cleanup
|
||||
%64 = icmp sge i8 trunc (i64 add (i64 and (i64 ptrtoint (i32* @b to i64), i64 7), i64 3) to i8), %61
|
||||
br i1 %64, label %65, label %66
|
||||
|
||||
; <label>:65: ; preds = %63
|
||||
call void @__asan_report_load4(i64 ptrtoint (i32* @b to i64))
|
||||
call void asm sideeffect "", ""()
|
||||
unreachable
|
||||
|
||||
; <label>:66: ; preds = %63, %cleanup
|
||||
%67 = load i32, i32* @b, align 4
|
||||
call void @__sanitizer_cov_trace_cmp4(i32 %67, i32 0)
|
||||
%tobool3 = icmp eq i32 %67, 0
|
||||
br i1 %tobool3, label %cleanup.while.cond.outer_crit_edge, label %cleanup.enoent.loopexit96_crit_edge
|
||||
|
||||
cleanup.enoent.loopexit96_crit_edge: ; preds = %66
|
||||
%68 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 20) to i32*) monotonic, align 4
|
||||
%69 = icmp sge i32 0, %68
|
||||
br i1 %69, label %70, label %71
|
||||
|
||||
; <label>:70: ; preds = %cleanup.enoent.loopexit96_crit_edge
|
||||
call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 20) to i32*))
|
||||
call void asm sideeffect "", ""()
|
||||
br label %71
|
||||
|
||||
; <label>:71: ; preds = %cleanup.enoent.loopexit96_crit_edge, %70
|
||||
br label %enoent.loopexit96
|
||||
|
||||
cleanup.while.cond.outer_crit_edge: ; preds = %66
|
||||
%72 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 24) to i32*) monotonic, align 4
|
||||
%73 = icmp sge i32 0, %72
|
||||
br i1 %73, label %74, label %75
|
||||
|
||||
; <label>:74: ; preds = %cleanup.while.cond.outer_crit_edge
|
||||
call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 24) to i32*))
|
||||
call void asm sideeffect "", ""()
|
||||
br label %75
|
||||
|
||||
; <label>:75: ; preds = %cleanup.while.cond.outer_crit_edge, %74
|
||||
br label %while.cond.outer
|
||||
|
||||
enoent.loopexit: ; preds = %51
|
||||
%76 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 28) to i32*) monotonic, align 4
|
||||
%77 = icmp sge i32 0, %76
|
||||
br i1 %77, label %78, label %79
|
||||
|
||||
; <label>:78: ; preds = %enoent.loopexit
|
||||
call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 28) to i32*))
|
||||
call void asm sideeffect "", ""()
|
||||
br label %79
|
||||
|
||||
; <label>:79: ; preds = %enoent.loopexit, %78
|
||||
br label %enoent
|
||||
|
||||
enoent.loopexit96: ; preds = %71, %20
|
||||
br label %enoent
|
||||
|
||||
enoent: ; preds = %enoent.loopexit96, %79, %60
|
||||
%call22 = tail call i32* (...) @fn1() #2
|
||||
br label %cleanup23
|
||||
|
||||
cleanup23.loopexit: ; preds = %25
|
||||
%80 = load atomic i32, i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 32) to i32*) monotonic, align 4
|
||||
%81 = icmp sge i32 0, %80
|
||||
br i1 %81, label %82, label %83
|
||||
|
||||
; <label>:82: ; preds = %cleanup23.loopexit
|
||||
call void @__sanitizer_cov(i32* inttoptr (i64 add (i64 ptrtoint ([9 x i32]* @__sancov_gen_cov to i64), i64 32) to i32*))
|
||||
call void asm sideeffect "", ""()
|
||||
br label %83
|
||||
|
||||
; <label>:83: ; preds = %cleanup23.loopexit, %82
|
||||
br label %cleanup23
|
||||
|
||||
cleanup23: ; preds = %83, %enoent
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @fn3(...) local_unnamed_addr #1
|
||||
|
||||
declare i32 @fn4(...) local_unnamed_addr #1
|
||||
|
||||
declare i32* @fn1(...) local_unnamed_addr #1
|
||||
|
||||
declare void @__sanitizer_cov(i32*)
|
||||
|
||||
declare void @__sanitizer_cov_trace_cmp1(i8, i8)
|
||||
|
||||
declare void @__sanitizer_cov_trace_cmp4(i32, i32)
|
||||
|
||||
declare void @__asan_report_load1(i64)
|
||||
|
||||
declare void @__asan_report_load4(i64)
|
||||
|
||||
declare void @__asan_report_load8(i64)
|
||||
|
||||
declare void @__asan_report_store4(i64)
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
; RUN: llc -regalloc=greedy -mtriple=x86_64-unknown-linux-gnu < %s -o - | FileCheck %s
|
||||
;
|
||||
; The test is to check no redundent mov as follows will be generated in %while.body loop.
|
||||
; .LBB0_2:
|
||||
; movsbl %cl, %ecx
|
||||
; movl %edx, %eax ==> This movl can be promoted outside of loop.
|
||||
; shll $5, %eax
|
||||
; ...
|
||||
; movl %eax, %edx
|
||||
; jne .LBB0_2
|
||||
;
|
||||
; CHECK-LABEL: foo:
|
||||
; CHECK: [[L0:.LBB0_[0-9]+]]: # %while.body
|
||||
; CHECK: movl %[[REGA:.*]], %[[REGB:.*]]
|
||||
; CHECK-NOT: movl %[[REGB]], %[[REGA]]
|
||||
; CHECK: jne [[L0]]
|
||||
;
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
|
||||
@b = common local_unnamed_addr global i8* null, align 8
|
||||
@a = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
define i32 @foo() local_unnamed_addr {
|
||||
entry:
|
||||
%t0 = load i8*, i8** @b, align 8
|
||||
%t1 = load i8, i8* %t0, align 1
|
||||
%cmp4 = icmp eq i8 %t1, 0
|
||||
%t2 = load i32, i32* @a, align 4
|
||||
br i1 %cmp4, label %while.end, label %while.body.preheader
|
||||
|
||||
while.body.preheader: ; preds = %entry
|
||||
br label %while.body
|
||||
|
||||
while.body: ; preds = %while.body.preheader, %while.body
|
||||
%t3 = phi i32 [ %add3, %while.body ], [ %t2, %while.body.preheader ]
|
||||
%t4 = phi i8 [ %t5, %while.body ], [ %t1, %while.body.preheader ]
|
||||
%conv = sext i8 %t4 to i32
|
||||
%add = mul i32 %t3, 33
|
||||
%add3 = add nsw i32 %add, %conv
|
||||
store i32 %add3, i32* @a, align 4
|
||||
%t5 = load i8, i8* %t0, align 1
|
||||
%cmp = icmp eq i8 %t5, 0
|
||||
br i1 %cmp, label %while.end.loopexit, label %while.body
|
||||
|
||||
while.end.loopexit: ; preds = %while.body
|
||||
br label %while.end
|
||||
|
||||
while.end: ; preds = %while.end.loopexit, %entry
|
||||
%.lcssa = phi i32 [ %t2, %entry ], [ %add3, %while.end.loopexit ]
|
||||
ret i32 %.lcssa
|
||||
}
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass simple-register-coalescing -o - %s | FileCheck %s
|
||||
# Check there is no partial redundent copy left in the loop after register coalescing.
|
||||
--- |
|
||||
; ModuleID = '<stdin>'
|
||||
source_filename = "<stdin>"
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
@b = common local_unnamed_addr global i8* null, align 8
|
||||
@a = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
define i32 @foo() local_unnamed_addr {
|
||||
entry:
|
||||
%t0 = load i8*, i8** @b, align 8
|
||||
%t1 = load i8, i8* %t0, align 1
|
||||
%cmp4 = icmp eq i8 %t1, 0
|
||||
%t2 = load i32, i32* @a, align 4
|
||||
br i1 %cmp4, label %while.end, label %while.body.preheader
|
||||
|
||||
while.body.preheader: ; preds = %entry
|
||||
br label %while.body
|
||||
|
||||
while.body: ; preds = %while.body, %while.body.preheader
|
||||
%t3 = phi i32 [ %add3, %while.body ], [ %t2, %while.body.preheader ]
|
||||
%t4 = phi i8 [ %t5, %while.body ], [ %t1, %while.body.preheader ]
|
||||
%conv = sext i8 %t4 to i32
|
||||
%add = mul i32 %t3, 33
|
||||
%add3 = add nsw i32 %add, %conv
|
||||
store i32 %add3, i32* @a, align 4
|
||||
%t5 = load i8, i8* %t0, align 1
|
||||
%cmp = icmp eq i8 %t5, 0
|
||||
br i1 %cmp, label %while.end, label %while.body
|
||||
|
||||
while.end: ; preds = %while.body, %entry
|
||||
%.lcssa = phi i32 [ %t2, %entry ], [ %add3, %while.body ]
|
||||
ret i32 %.lcssa
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
# Check A = B and B = A copies will not exist in the loop at the same time.
|
||||
# CHECK: name: foo
|
||||
# CHECK: [[L1:bb.3.while.body]]:
|
||||
# CHECK: %[[REGA:.*]] = COPY %[[REGB:.*]]
|
||||
# CHECK-NOT: %[[REGB]] = COPY %[[REGA]]
|
||||
# CHECK: JNE_1 %[[L1]]
|
||||
|
||||
name: foo
|
||||
alignment: 4
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gr64 }
|
||||
- { id: 1, class: gr8 }
|
||||
- { id: 2, class: gr32 }
|
||||
- { id: 3, class: gr32 }
|
||||
- { id: 4, class: gr8 }
|
||||
- { id: 5, class: gr32 }
|
||||
- { id: 6, class: gr8 }
|
||||
- { id: 7, class: gr32 }
|
||||
- { id: 8, class: gr32 }
|
||||
- { id: 9, class: gr32 }
|
||||
- { id: 10, class: gr32 }
|
||||
- { id: 11, class: gr32 }
|
||||
- { id: 12, class: gr8 }
|
||||
- { id: 13, class: gr32 }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.4(0x30000000), %bb.1.while.body.preheader(0x50000000)
|
||||
|
||||
%0 = MOV64rm %rip, 1, _, @b, _ :: (dereferenceable load 8 from @b)
|
||||
%12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
|
||||
TEST8rr %12, %12, implicit-def %eflags
|
||||
%11 = MOV32rm %rip, 1, _, @a, _ :: (dereferenceable load 4 from @a)
|
||||
JNE_1 %bb.1.while.body.preheader, implicit killed %eflags
|
||||
|
||||
bb.4:
|
||||
successors: %bb.3.while.end(0x80000000)
|
||||
|
||||
%10 = COPY %11
|
||||
JMP_1 %bb.3.while.end
|
||||
|
||||
bb.1.while.body.preheader:
|
||||
successors: %bb.2.while.body(0x80000000)
|
||||
|
||||
bb.2.while.body:
|
||||
successors: %bb.3.while.end(0x04000000), %bb.2.while.body(0x7c000000)
|
||||
|
||||
%8 = MOVSX32rr8 %12
|
||||
%10 = COPY %11
|
||||
%10 = SHL32ri %10, 5, implicit-def dead %eflags
|
||||
%10 = ADD32rr %10, %11, implicit-def dead %eflags
|
||||
%10 = ADD32rr %10, %8, implicit-def dead %eflags
|
||||
MOV32mr %rip, 1, _, @a, _, %10 :: (store 4 into @a)
|
||||
%12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
|
||||
TEST8rr %12, %12, implicit-def %eflags
|
||||
%11 = COPY %10
|
||||
JNE_1 %bb.2.while.body, implicit killed %eflags
|
||||
JMP_1 %bb.3.while.end
|
||||
|
||||
bb.3.while.end:
|
||||
%eax = COPY %10
|
||||
RET 0, killed %eax
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue