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[X86] Use VEX_WIG for VPINSRB/W and VPEXTRB/W to match what is done for EVEX. 

The instruction's document this as W0 for the VEX encoding. But there's a
footnote mentioning that VEX.W is ignored in 64-bit mode. And the main VEX
encoding description says the VEX.W bit is ignored for instructions that are
equivalent to a legacy SSE instruction that uses REX.W to select a GPR which
would apply here.

By making this match EVEX we can remove a special case of allowing EVEX2VEX to
turn an EVEX.WIG instruction into VEX.W0.

llvm-svn: 357971
This commit is contained in:
Craig Topper 2019-04-09 07:40:10 +00:00
parent 2f9c1732b8
commit f19f991b7f
2 changed files with 6 additions and 6 deletions
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10
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -4052,7 +4052,7 @@ def VPEXTRWrr : Ii8<0xC5, MRMSrcReg,
"vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
imm:$src2))]>, imm:$src2))]>,
PD, VEX, Sched<[WriteVecExtract]>; PD, VEX, VEX_WIG, Sched<[WriteVecExtract]>;
def PEXTRWrr : PDIi8<0xC5, MRMSrcReg, def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
(outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@ -4062,7 +4062,7 @@ def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
// Insert // Insert
let Predicates = [HasAVX, NoBWI] in let Predicates = [HasAVX, NoBWI] in
defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V; defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V, VEX_WIG;
let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
defm PINSRW : sse2_pinsrw, PD; defm PINSRW : sse2_pinsrw, PD;
@ -5362,7 +5362,7 @@ multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
} }
let Predicates = [HasAVX, NoBWI] in let Predicates = [HasAVX, NoBWI] in
defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX; defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX, VEX_WIG;
defm PEXTRB : SS41I_extract8<0x14, "pextrb">; defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
@ -5386,7 +5386,7 @@ multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
} }
let Predicates = [HasAVX, NoBWI] in let Predicates = [HasAVX, NoBWI] in
defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX; defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX, VEX_WIG;
defm PEXTRW : SS41I_extract16<0x15, "pextrw">; defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
@ -5485,7 +5485,7 @@ multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
} }
let Predicates = [HasAVX, NoBWI] in let Predicates = [HasAVX, NoBWI] in
defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V; defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V, VEX_WIG;
let Constraints = "$src1 = $dst" in let Constraints = "$src1 = $dst" in
defm PINSRB : SS41I_insert8<0x20, "pinsrb">; defm PINSRB : SS41I_insert8<0x20, "pinsrb">;

2
llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
View File

@ -123,7 +123,7 @@ public:
RecE->getValueAsBitsInit("EVEX_LL")) || RecE->getValueAsBitsInit("EVEX_LL")) ||
// Match is allowed if either is VEX_WIG, or they match, or EVEX // Match is allowed if either is VEX_WIG, or they match, or EVEX
// is VEX_W1X and VEX is VEX_W0. // is VEX_W1X and VEX is VEX_W0.
(!(VEX_WIG || EVEX_WIG || EVEX_W == VEX_W || (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
(EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) || (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
// Instruction's format // Instruction's format
RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form") || RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form") ||