forked from OSchip/llvm-project
Move the code that inserts copies for function livein registers
out of ScheduleDAGEmit.cpp and into SelectionDAGISel.cpp. This allows it to be run exactly once per function, even if multiple SelectionDAG iterations happen in the entry block, as may happen with FastISel. llvm-svn: 55863
This commit is contained in:
Dan Gohman
parent
8de9c3affe
commit
f17a2f3602
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@ -30,13 +30,6 @@ using namespace llvm;
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STATISTIC(NumCommutes, "Number of instructions commuted");
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namespace {
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static cl::opt<bool>
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SchedLiveInCopies("schedule-livein-copies",
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cl::desc("Schedule copies of livein registers"),
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cl::init(false));
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}
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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@ -653,100 +646,8 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
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}
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}
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible.
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void ScheduleDAG::EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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DenseMap<MachineInstr*, unsigned> &CopyRegMap){
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unsigned NumUses = 0;
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MachineInstr *UseMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
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UE = MRI.use_end(); UI != UE; ++UI) {
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UseMI = &*UI;
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if (++NumUses > 1)
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break;
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}
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// If the number of uses is not one, or the use is not a move instruction,
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// don't coalesce. Also, only coalesce away a virtual register to virtual
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// register copy.
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bool Coalesced = false;
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unsigned SrcReg, DstReg;
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if (NumUses == 1 &&
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TII->isMoveInstr(*UseMI, SrcReg, DstReg) &&
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TargetRegisterInfo::isVirtualRegister(DstReg)) {
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VirtReg = DstReg;
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Coalesced = true;
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}
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// Now find an ideal location to insert the copy.
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MachineBasicBlock::iterator Pos = InsertPos;
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while (Pos != MBB->begin()) {
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MachineInstr *PrevMI = prior(Pos);
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DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
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// copyRegToReg might emit multiple instructions to do a copy.
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unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
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if (CopyDstReg && !TRI->regsOverlap(CopyDstReg, PhysReg))
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// This is what the BB looks like right now:
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// r1024 = mov r0
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// ...
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// r1 = mov r1024
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//
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// We want to insert "r1025 = mov r1". Inserting this copy below the
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// move to r1024 makes it impossible for that move to be coalesced.
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//
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// r1025 = mov r1
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// r1024 = mov r0
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// ...
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// r1 = mov 1024
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// r2 = mov 1025
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break; // Woot! Found a good location.
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--Pos;
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}
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TII->copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
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CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
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if (Coalesced) {
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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}
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}
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/// EmitLiveInCopies - If this is the first basic block in the function,
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/// and if it has live ins that need to be copied into vregs, emit the
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/// copies into the top of the block.
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void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
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DenseMap<MachineInstr*, unsigned> CopyRegMap;
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MachineBasicBlock::iterator InsertPos = MBB->begin();
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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EmitLiveInCopy(MBB, InsertPos, LI->second, LI->first, RC, CopyRegMap);
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}
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}
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/// EmitSchedule - Emit the machine code in scheduled order.
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MachineBasicBlock *ScheduleDAG::EmitSchedule() {
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bool isEntryBB = &MF->front() == BB;
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if (isEntryBB && !SchedLiveInCopies) {
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// If this is the first basic block in the function, and if it has live ins
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// that need to be copied into vregs, emit the copies into the top of the
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// block before emitting the code for the block.
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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TII->copyRegToReg(*MF->begin(), MF->begin()->end(), LI->second,
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LI->first, RC, RC);
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}
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}
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// Finally, emit the code for all of the scheduled instructions.
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DenseMap<SDValue, unsigned> VRBaseMap;
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DenseMap<SUnit*, unsigned> CopyVRBaseMap;
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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@ -764,8 +665,5 @@ MachineBasicBlock *ScheduleDAG::EmitSchedule() {
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EmitNode(SU->Node, SU->OrigNode != SU, VRBaseMap);
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}
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if (isEntryBB && SchedLiveInCopies)
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EmitLiveInCopies(MF->begin());
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return BB;
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}
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@ -63,6 +63,10 @@ static cl::opt<bool>
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DisableFastISelAbort("fast-isel-no-abort", cl::Hidden,
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cl::desc("Use the SelectionDAGISel when \"fast\" instruction "
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"selection fails"));
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static cl::opt<bool>
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SchedLiveInCopies("schedule-livein-copies",
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cl::desc("Schedule copies of livein registers"),
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cl::init(false));
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#ifndef NDEBUG
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static cl::opt<bool>
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@ -153,6 +157,101 @@ MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return 0;
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}
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible.
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static void EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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DenseMap<MachineInstr*, unsigned> &CopyRegMap,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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unsigned NumUses = 0;
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MachineInstr *UseMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
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UE = MRI.use_end(); UI != UE; ++UI) {
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UseMI = &*UI;
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if (++NumUses > 1)
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break;
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}
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// If the number of uses is not one, or the use is not a move instruction,
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// don't coalesce. Also, only coalesce away a virtual register to virtual
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// register copy.
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bool Coalesced = false;
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unsigned SrcReg, DstReg;
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if (NumUses == 1 &&
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TII.isMoveInstr(*UseMI, SrcReg, DstReg) &&
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TargetRegisterInfo::isVirtualRegister(DstReg)) {
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VirtReg = DstReg;
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Coalesced = true;
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}
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// Now find an ideal location to insert the copy.
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MachineBasicBlock::iterator Pos = InsertPos;
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while (Pos != MBB->begin()) {
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MachineInstr *PrevMI = prior(Pos);
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DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
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// copyRegToReg might emit multiple instructions to do a copy.
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unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
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if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
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// This is what the BB looks like right now:
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// r1024 = mov r0
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// ...
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// r1 = mov r1024
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//
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// We want to insert "r1025 = mov r1". Inserting this copy below the
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// move to r1024 makes it impossible for that move to be coalesced.
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//
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// r1025 = mov r1
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// r1024 = mov r0
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// ...
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// r1 = mov 1024
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// r2 = mov 1025
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break; // Woot! Found a good location.
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--Pos;
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}
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TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
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CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
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if (Coalesced) {
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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}
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}
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/// EmitLiveInCopies - If this is the first basic block in the function,
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/// and if it has live ins that need to be copied into vregs, emit the
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/// copies into the block.
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static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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if (SchedLiveInCopies) {
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// Emit the copies at a heuristically-determined location in the block.
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DenseMap<MachineInstr*, unsigned> CopyRegMap;
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MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
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RC, CopyRegMap, MRI, TRI, TII);
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}
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} else {
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// Emit the copies into the top of the block.
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
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LI->second, LI->first, RC, RC);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// SelectionDAGISel code
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//===----------------------------------------------------------------------===//
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@ -187,7 +286,12 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
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// Get alias analysis for load/store combining.
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AA = &getAnalysis<AliasAnalysis>();
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MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
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TargetMachine &TM = TLI.getTargetMachine();
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MachineFunction &MF = MachineFunction::construct(&Fn, TM);
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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if (MF.getFunction()->hasGC())
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GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
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else
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@ -206,13 +310,15 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
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SelectAllBasicBlocks(Fn, MF);
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// If the first basic block in the function has live ins that need to be
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// copied into vregs, emit the copies into the top of the block before
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// emitting the code for the block.
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EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
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// Add function live-ins to entry block live-in set.
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BasicBlock *EntryBB = &Fn.getEntryBlock();
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BB = FuncInfo->MBBMap[EntryBB];
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if (!RegInfo->livein_empty())
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for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
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E = RegInfo->livein_end(); I != E; ++I)
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BB->addLiveIn(I->first);
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for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
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E = RegInfo->livein_end(); I != E; ++I)
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MF.begin()->addLiveIn(I->first);
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#ifndef NDEBUG
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assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
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