forked from OSchip/llvm-project
parent
8c60bc9211
commit
f14032af0e
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@ -367,7 +367,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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return true;
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return true;
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}
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}
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unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
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unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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switch (MI.getOpcode()) {
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default: return AMDGPU::INSTRUCTION_LIST_END;
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default: return AMDGPU::INSTRUCTION_LIST_END;
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case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
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case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
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@ -68,7 +68,7 @@ public:
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StringRef &ErrInfo) const;
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StringRef &ErrInfo) const;
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bool isSALUInstr(const MachineInstr &MI) const;
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bool isSALUInstr(const MachineInstr &MI) const;
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unsigned getVALUOp(const MachineInstr &MI) const;
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static unsigned getVALUOp(const MachineInstr &MI);
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bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
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bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
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/// \brief Return the correct register class for \p OpNo. For target-specific
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/// \brief Return the correct register class for \p OpNo. For target-specific
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