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[Pipeliner] Fix assert caused by pipeliner serialization 

The pipeliner is asserting because the serialization step that 
occurs at the end is deleting an instruction.  The assert
occurs later on because there is a use without a definition.  

The problem occurs when an instruction defines a value used 
by a REQ_SEQUENCE and that value is used by a COPY instruction.
The latencies between these instructions are zero, so they are
put in to the same packet.  The serialization code is unable to
handle this correctly, and ends up putting the REG_SEQUENCE
before its definition.

There is special code in the serialization step that attempts
to handle zero-cost instructions (phis, copy, reg_sequence)
differently than regular instructions. Unfortunately, this means
the order does not come out correct.

This patch simplifies the code by changing the seperate steps for
handling zero-cost and regular instructions. Only phis are
handled separate now, since they should occurs first. Then, this
patch adds checks to make use the MoveUse is set to the smallest
value if there are multiple uses in a cycle.

Patch by Brendon Cahoon.

llvm-svn: 328540
This commit is contained in:
Krzysztof Parzyszek 2018-03-26 16:23:29 +00:00
parent d870aea03e
commit f13bbf1d58
2 changed files with 52 additions and 28 deletions
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51
llvm/lib/CodeGen/MachinePipeliner.cpp
View File

@ -702,7 +702,7 @@ public:
bool isValidSchedule(SwingSchedulerDAG *SSD);
void finalizeSchedule(SwingSchedulerDAG *SSD);
bool orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
std::deque<SUnit *> &Insts);
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi);
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Inst,
@ -3745,7 +3745,7 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
/// Order the instructions within a cycle so that the definitions occur
/// before the uses. Returns true if the instruction is added to the start
/// of the list, or false if added to the end.
bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
void SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
std::deque<SUnit *> &Insts) {
MachineInstr *MI = SU->getInstr();
bool OrderBeforeUse = false;
@ -3758,13 +3758,11 @@ bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
unsigned Pos = 0;
for (std::deque<SUnit *>::iterator I = Insts.begin(), E = Insts.end(); I != E;
++I, ++Pos) {
// Relative order of Phis does not matter.
if (MI->isPHI() && (*I)->getInstr()->isPHI())
continue;
for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue;
unsigned Reg = MO.getReg();
unsigned BasePos, OffsetPos;
if (ST.getInstrInfo()->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
@ -3776,7 +3774,8 @@ bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
(*I)->getInstr()->readsWritesVirtualRegister(Reg);
if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
OrderBeforeUse = true;
MoveUse = Pos;
if (MoveUse == 0)
MoveUse = Pos;
} else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) {
// Add the instruction after the scheduled instruction.
OrderAfterDef = true;
@ -3784,14 +3783,16 @@ bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
} else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
if (cycleScheduled(*I) == cycleScheduled(SU) && !(*I)->isSucc(SU)) {
OrderBeforeUse = true;
MoveUse = Pos;
if (MoveUse == 0)
MoveUse = Pos;
} else {
OrderAfterDef = true;
MoveDef = Pos;
}
} else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
OrderBeforeUse = true;
MoveUse = Pos;
if (MoveUse == 0)
MoveUse = Pos;
if (MoveUse != 0) {
OrderAfterDef = true;
MoveDef = Pos - 1;
@ -3799,11 +3800,14 @@ bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
} else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
// Add the instruction before the scheduled instruction.
OrderBeforeUse = true;
MoveUse = Pos;
if (MoveUse == 0)
MoveUse = Pos;
} else if (MO.isUse() && stageScheduled(*I) == StageInst1 &&
isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {
OrderBeforeDef = true;
MoveUse = Pos;
if (MoveUse == 0) {
OrderBeforeDef = true;
MoveUse = Pos;
}
}
}
// Check for order dependences between instructions. Make sure the source
@ -3848,16 +3852,10 @@ bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
Insts.erase(Insts.begin() + MoveDef);
Insts.erase(Insts.begin() + MoveUse);
}
if (orderDependence(SSD, UseSU, Insts)) {
Insts.push_front(SU);
orderDependence(SSD, DefSU, Insts);
return true;
}
Insts.pop_back();
Insts.push_back(SU);
Insts.push_back(UseSU);
orderDependence(SSD, UseSU, Insts);
orderDependence(SSD, SU, Insts);
orderDependence(SSD, DefSU, Insts);
return false;
return;
}
// Put the new instruction first if there is a use in the list. Otherwise,
// put it at the end of the list.
@ -3865,7 +3863,6 @@ bool SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
Insts.push_front(SU);
else
Insts.push_back(SU);
return OrderBeforeUse;
}
/// Return true if the scheduled Phi has a loop carried operand.
@ -4151,22 +4148,20 @@ void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {
// generated code.
for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) {
std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle];
std::deque<SUnit *> newOrderZC;
// Put the zero-cost, pseudo instructions at the start of the cycle.
std::deque<SUnit *> newOrderPhi;
for (unsigned i = 0, e = cycleInstrs.size(); i < e; ++i) {
SUnit *SU = cycleInstrs[i];
if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()))
orderDependence(SSD, SU, newOrderZC);
if (SU->getInstr()->isPHI())
newOrderPhi.push_back(SU);
}
std::deque<SUnit *> newOrderI;
// Then, add the regular instructions back.
for (unsigned i = 0, e = cycleInstrs.size(); i < e; ++i) {
SUnit *SU = cycleInstrs[i];
if (!ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()))
if (!SU->getInstr()->isPHI())
orderDependence(SSD, SU, newOrderI);
}
// Replace the old order with the new order.
cycleInstrs.swap(newOrderZC);
cycleInstrs.swap(newOrderPhi);
cycleInstrs.insert(cycleInstrs.end(), newOrderI.begin(), newOrderI.end());
SSD->fixupRegisterOverlaps(cycleInstrs);
}

29
llvm/test/CodeGen/Hexagon/swp-order-deps5.ll Normal file
View File

@ -0,0 +1,29 @@
; RUN: llc -march=hexagon -hexagon-bit=0 < %s
; REQUIRES: asserts
; Function Attrs: nounwind
define void @f0() local_unnamed_addr #0 {
b0:
br label %b1
b1: ; preds = %b1, %b0
%v0 = phi i32 [ 1, %b0 ], [ %v9, %b1 ]
%v1 = phi i64 [ 0, %b0 ], [ %v10, %b1 ]
%v2 = load i32, i32* undef, align 4
%v3 = sub nsw i32 0, %v2
%v4 = select i1 undef, i32 undef, i32 %v3
%v5 = sext i32 %v4 to i64
%v6 = mul nsw i64 %v5, %v5
%v7 = or i64 %v1, 0
%v8 = add i64 %v6, %v7
%v9 = add nuw nsw i32 %v0, 1
%v10 = and i64 %v8, -4294967296
%v11 = icmp ult i32 %v9, undef
br i1 %v11, label %b1, label %b2
b2: ; preds = %b1
%v12 = sdiv i64 %v8, undef
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv62" }