maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Fix up some problems with getCopyToReg and getCopyFromReg nodes being 

chained and "flagged" together.  I also made a few changes to handle the
chain and flag values more consistently.  I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).

llvm-svn: 69977
This commit is contained in:
Bob Wilson 2009-04-24 17:00:36 +00:00
parent 33e834cc0a
commit f134b2d212
1 changed files with 12 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -504,23 +504,26 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
if (VA.needsCustom()) { if (VA.needsCustom()) {
SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
InFlag); InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc VA = RVLocs[++i]; // skip ahead to next loc
SDValue Hi = DAG.getCopyFromReg(Lo, dl, VA.getLocReg(), VA.getLocVT(), SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
Lo.getValue(2)); InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, VA.getValVT(), Lo, ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, VA.getValVT(), Lo,
Hi)); Hi));
} else { } else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
InFlag).getValue(1); InFlag);
SDValue Val = Chain.getValue(0); Chain = Val.getValue(1);
InFlag = Chain.getValue(2); InFlag = Val.getValue(2);
switch (VA.getLocInfo()) { switch (VA.getLocInfo()) {
default: assert(0 && "Unknown loc info!"); default: assert(0 && "Unknown loc info!");
case CCValAssign::Full: break; case CCValAssign::Full: break;
case CCValAssign::BCvt: case CCValAssign::BCvt:
Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
Chain.getValue(0));
break; break;
} }
@ -813,6 +816,7 @@ SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
Flag = Chain.getValue(1);
VA = RVLocs[++i]; // skip ahead to next loc VA = RVLocs[++i]; // skip ahead to next loc
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
Flag); Flag);