forked from OSchip/llvm-project
[WebAssembly] Lower vselect to v128.bitselect
We were previously expanding vselect and matching on the expansion to generate bitselects, but in some cases the expansion would be further combined and a bitselect would not get generated. This patch improves codegen in those cases by legalizing vselect and lowering it to v128.bitselect. The old pattern that matches the expansion is still useful for lowering IR that already uses the expansion rather than a select operation. Differential Revision: https://reviews.llvm.org/D83734
This commit is contained in:
Thomas Lively
parent
9adf7461f7
commit
f0f9787646
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@ -156,8 +156,9 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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// There is no i8x16.mul instruction
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setOperationAction(ISD::MUL, MVT::v16i8, Expand);
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// There are no vector select instructions
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for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT})
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// There is no vector conditional select instruction
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// TODO: Implement SELECT_V128
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for (auto Op : {ISD::SELECT_CC, ISD::SELECT})
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for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
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MVT::v2f64})
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setOperationAction(Op, T, Expand);
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@ -574,6 +574,16 @@ foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
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(!cast<Instruction>("BITSELECT_"#vec_t)
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V128:$v1, V128:$v2, V128:$c)>;
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// Also implement vselect in terms of bitselect
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foreach types = [[v16i8, v16i8], [v8i16, v8i16], [v4i32, v4i32], [v2i64, v2i64],
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[v4f32, v4i32], [v2f64, v2i64]] in
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def : Pat<(types[0] (vselect
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(types[1] V128:$c), (types[0] V128:$v1), (types[0] V128:$v2)
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)),
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(!cast<Instruction>("BITSELECT_"#types[0])
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V128:$v1, V128:$v2, V128:$c
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)>;
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//===----------------------------------------------------------------------===//
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// Integer unary arithmetic
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//===----------------------------------------------------------------------===//
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@ -21,6 +21,18 @@ define <16 x i8> @vselect_v16i8(<16 x i1> %c, <16 x i8> %x, <16 x i8> %y) {
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ret <16 x i8> %res
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}
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; CHECK-LABEL: vselect_cmp_v16i8:
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; CHECK-NEXT: .functype vselect_cmp_v16i8 (v128, v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i8x16.lt_s $push[[L0:[0-9]+]]=, $0, $1{{$}}
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; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $3, $pop[[L0]]{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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define <16 x i8> @vselect_cmp_v16i8(<16 x i8> %a, <16 x i8> %b,
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<16 x i8> %x, <16 x i8> %y) {
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%c = icmp slt <16 x i8> %a, %b
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%res = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y
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ret <16 x i8> %res
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}
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; CHECK-LABEL: select_v16i8:
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; CHECK-NEXT: .functype select_v16i8 (i32, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
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@ -91,6 +103,18 @@ define <8 x i16> @vselect_v8i16(<8 x i1> %c, <8 x i16> %x, <8 x i16> %y) {
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ret <8 x i16> %res
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}
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; CHECK-LABEL: vselect_cmp_v8i16:
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; CHECK-NEXT: .functype vselect_cmp_v8i16 (v128, v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i16x8.lt_s $push[[L0:[0-9]+]]=, $0, $1{{$}}
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; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $3, $pop[[L0]]{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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define <8 x i16> @vselect_cmp_v8i16(<8 x i16> %a, <8 x i16> %b,
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<8 x i16> %x, <8 x i16> %y) {
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%c = icmp slt <8 x i16> %a, %b
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%res = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y
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ret <8 x i16> %res
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}
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; CHECK-LABEL: select_v8i16:
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; CHECK-NEXT: .functype select_v8i16 (i32, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
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@ -161,6 +185,17 @@ define <4 x i32> @vselect_v4i32(<4 x i1> %c, <4 x i32> %x, <4 x i32> %y) {
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ret <4 x i32> %res
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}
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; CHECK-LABEL: vselect_cmp_v4i32:
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; CHECK-NEXT: .functype vselect_cmp_v4i32 (v128, v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i32x4.lt_s $push[[L0:[0-9]+]]=, $0, $1{{$}}
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; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $3, $pop[[L0]]{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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define <4 x i32> @vselect_cmp_v4i32(<4 x i32> %a, <4 x i32> %b,
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<4 x i32> %x, <4 x i32> %y) {
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%c = icmp slt <4 x i32> %a, %b
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%res = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %res
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}
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; CHECK-LABEL: select_v4i32:
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; CHECK-NEXT: .functype select_v4i32 (i32, v128, v128) -> (v128){{$}}
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@ -232,6 +267,31 @@ define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
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ret <2 x i64> %res
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}
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; CHECK-LABEL: vselect_cmp_v2i64:
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; CHECK-NEXT: .functype vselect_cmp_v2i64 (v128, v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
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; CHECK-NEXT: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
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; CHECK-NEXT: i64x2.extract_lane $push[[L2:[0-9]+]]=, $0, 0{{$}}
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; CHECK-NEXT: i64x2.extract_lane $push[[L3:[0-9]+]]=, $1, 0{{$}}
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; CHECK-NEXT: i64.lt_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
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; CHECK-NEXT: i64.select $push[[L5:[0-9]+]]=, $pop[[L0]], $pop[[L1]], $pop[[L4]]{{$}}
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; CHECK-NEXT: i64x2.splat $push[[L6:[0-9]+]]=, $pop[[L5]]{{$}}
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; CHECK-NEXT: i64.const $push[[L7:[0-9]+]]=, -1{{$}}
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; CHECK-NEXT: i64.const $push[[L8:[0-9]+]]=, 0{{$}}
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; CHECK-NEXT: i64x2.extract_lane $push[[L9:[0-9]+]]=, $0, 1{{$}}
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; CHECK-NEXT: i64x2.extract_lane $push[[L10:[0-9]+]]=, $1, 1{{$}}
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; CHECK-NEXT: i64.lt_s $push[[L11:[0-9]+]]=, $pop[[L9]], $pop[[L10]]{{$}}
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; CHECK-NEXT: i64.select $push[[L12:[0-9]+]]=, $pop[[L7]], $pop[[L8]], $pop[[L11]]{{$}}
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; CHECK-NEXT: i64x2.replace_lane $push[[L13:[0-9]+]]=, $pop[[L6]], 1, $pop[[L12]]{{$}}
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; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $3, $pop[[L13]]{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @vselect_cmp_v2i64(<2 x i64> %a, <2 x i64> %b,
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<2 x i64> %x, <2 x i64> %y) {
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%c = icmp slt <2 x i64> %a, %b
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%res = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %y
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ret <2 x i64> %res
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}
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; CHECK-LABEL: select_v2i64:
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; CHECK-NEXT: .functype select_v2i64 (i32, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
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@ -305,6 +365,18 @@ define <4 x float> @vselect_v4f32(<4 x i1> %c, <4 x float> %x, <4 x float> %y) {
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ret <4 x float> %res
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}
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; CHECK-LABEL: vselect_cmp_v4f32:
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; CHECK-NEXT: .functype vselect_cmp_v4f32 (v128, v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: f32x4.lt $push[[L0:[0-9]+]]=, $0, $1{{$}}
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; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $3, $pop[[L0]]{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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define <4 x float> @vselect_cmp_v4f32(<4 x float> %a, <4 x float> %b,
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<4 x float> %x, <4 x float> %y) {
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%c = fcmp olt <4 x float> %a, %b
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%res = select <4 x i1> %c, <4 x float> %x, <4 x float> %y
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ret <4 x float> %res
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}
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; CHECK-LABEL: select_v4f32:
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; CHECK-NEXT: .functype select_v4f32 (i32, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, -1{{$}}
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@ -375,6 +447,18 @@ define <2 x double> @vselect_v2f64(<2 x i1> %c, <2 x double> %x, <2 x double> %y
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ret <2 x double> %res
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}
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; CHECK-LABEL: vselect_cmp_v2f64:
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; CHECK-NEXT: .functype vselect_cmp_v2f64 (v128, v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: f64x2.lt $push[[L0:[0-9]+]]=, $0, $1{{$}}
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; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $2, $3, $pop[[L0]]{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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define <2 x double> @vselect_cmp_v2f64(<2 x double> %a, <2 x double> %b,
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<2 x double> %x, <2 x double> %y) {
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%c = fcmp olt <2 x double> %a, %b
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%res = select <2 x i1> %c, <2 x double> %x, <2 x double> %y
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ret <2 x double> %res
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}
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; CHECK-LABEL: select_v2f64:
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; CHECK-NEXT: .functype select_v2f64 (i32, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i64.const $push[[L0:[0-9]+]]=, -1{{$}}
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