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[AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to integer operations when DQI isn't supported. This is consistent with the recent changes to promote logical operations to i64 vectors. 

llvm-svn: 279957
This commit is contained in:
Craig Topper 2016-08-29 04:49:27 +00:00
parent 71584cd0f0
commit f0e822ff31
1 changed files with 3 additions and 5 deletions
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8
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -30365,11 +30365,9 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
// VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
// These logic operations may be executed in the integer domain.
SDLoc dl(N);
MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
SDValue Op0 = DAG.getBitcast(IntVT, N->getOperand(0));
SDValue Op1 = DAG.getBitcast(IntVT, N->getOperand(1));
SDValue Op0 = DAG.getBitcast(MVT::v8i64, N->getOperand(0));
SDValue Op1 = DAG.getBitcast(MVT::v8i64, N->getOperand(1));
unsigned IntOpcode = 0;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected FP logic op");
@ -30378,7 +30376,7 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
case X86ISD::FAND: IntOpcode = ISD::AND; break;
case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
}
SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
SDValue IntOp = DAG.getNode(IntOpcode, dl, MVT::v8i64, Op0, Op1);
return DAG.getBitcast(VT, IntOp);
}
return SDValue();