forked from OSchip/llvm-project
X86: add costs for 64-bit vector ext/trunc & rebalance
The most important part of this is probably adding any cost at all for operations like zext <8 x i8> to <8 x i32>. Before they were being recorded as extremely costly (24, I believe) which made LLVM fall back on a 4-wide vectorisation of a loop. It also rebalances the values for sext, zext and trunc. Lacking any other sane metric that might work across CPU microarchitectures I went for instructions. This seems to be in reasonable accord with the rest of the table (sitofp, ...) though no doubt at least one value is sub-optimal for some bizarre reason. Finally, separate AVX and AVX2 values are provided where appropriate. The CodeGen is quite different in many cases. rdar://problem/15981990 llvm-svn: 200928
This commit is contained in:
Tim Northover
parent
e17f37082b
commit
f0e21616f3
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@ -411,16 +411,58 @@ unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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AVXConversionTbl[] = {
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AVX2ConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
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{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
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{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
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{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 },
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{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
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{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
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{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
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{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
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{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
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};
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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AVXConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
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{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
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{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
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{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
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{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
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{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
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{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
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{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
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@ -450,14 +492,15 @@ unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
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{ ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
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{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
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};
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if (ST->hasAVX2()) {
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int Idx = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return AVX2ConversionTbl[Idx].Cost;
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}
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if (ST->hasAVX()) {
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int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
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SrcTy.getSimpleVT());
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@ -1,10 +1,11 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
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; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AVX2
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; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AVX
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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define i32 @add(i32 %arg) {
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; CHECK-LABEL: for function 'add'
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; -- Same size registeres --
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;CHECK: cost of 1 {{.*}} zext
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%A = zext <4 x i1> undef to <4 x i32>
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@ -33,57 +34,106 @@ define i32 @add(i32 %arg) {
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}
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define i32 @zext_sext(<8 x i1> %in) {
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;CHECK: cost of 6 {{.*}} zext
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; CHECK-AVX2-LABEL: for function 'zext_sext'
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; CHECK-AVX-LABEL: for function 'zext_sext'
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;CHECK-AVX2: cost of 3 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%Z = zext <8 x i1> %in to <8 x i32>
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;CHECK: cost of 9 {{.*}} sext
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;CHECK-AVX2: cost of 3 {{.*}} sext
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;CHECK-AVX: cost of 7 {{.*}} sext
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%S = sext <8 x i1> %in to <8 x i32>
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;CHECK: cost of 1 {{.*}} zext
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;CHECK-AVX2: cost of 1 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%A1 = zext <16 x i8> undef to <16 x i16>
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;CHECK: cost of 1 {{.*}} sext
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;CHECK-AVX2: cost of 1 {{.*}} sext
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;CHECK-AVX: cost of 4 {{.*}} sext
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%A2 = sext <16 x i8> undef to <16 x i16>
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;CHECK: cost of 1 {{.*}} sext
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;CHECK-AVX2: cost of 1 {{.*}} sext
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;CHECK-AVX: cost of 4 {{.*}} sext
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%A = sext <8 x i16> undef to <8 x i32>
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;CHECK: cost of 1 {{.*}} zext
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;CHECK-AVX2: cost of 1 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%B = zext <8 x i16> undef to <8 x i32>
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;CHECK: cost of 1 {{.*}} sext
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;CHECK-AVX2: cost of 1 {{.*}} sext
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;CHECK-AVX: cost of 4 {{.*}} sext
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%C = sext <4 x i32> undef to <4 x i64>
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;CHECK: cost of 6 {{.*}} sext
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%C1 = sext <4 x i8> undef to <4 x i64>
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;CHECK: cost of 6 {{.*}} sext
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%C2 = sext <4 x i16> undef to <4 x i64>
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;CHECK: cost of 1 {{.*}} zext
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;CHECK-AVX2: cost of 3 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%C.v8i8.z = zext <8 x i8> undef to <8 x i32>
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;CHECK-AVX2: cost of 3 {{.*}} sext
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;CHECK-AVX: cost of 7 {{.*}} sext
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%C.v8i8.s = sext <8 x i8> undef to <8 x i32>
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;CHECK-AVX2: cost of 3 {{.*}} zext
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;CHECK-AVX: cost of 3 {{.*}} zext
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%C.v4i16.z = zext <4 x i16> undef to <4 x i64>
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;CHECK-AVX2: cost of 3 {{.*}} sext
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;CHECK-AVX: cost of 6 {{.*}} sext
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%C.v4i16.s = sext <4 x i16> undef to <4 x i64>
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;CHECK-AVX2: cost of 3 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%C.v4i8.z = zext <4 x i8> undef to <4 x i64>
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;CHECK-AVX2: cost of 3 {{.*}} sext
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;CHECK-AVX: cost of 6 {{.*}} sext
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%C.v4i8.s = sext <4 x i8> undef to <4 x i64>
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;CHECK-AVX2: cost of 1 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%D = zext <4 x i32> undef to <4 x i64>
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;CHECK: cost of 1 {{.*}} trunc
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;CHECK-AVX2: cost of 2 {{.*}} trunc
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;CHECK-AVX: cost of 4 {{.*}} trunc
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%E = trunc <4 x i64> undef to <4 x i32>
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;CHECK: cost of 1 {{.*}} trunc
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;CHECK-AVX2: cost of 2 {{.*}} trunc
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;CHECK-AVX: cost of 5 {{.*}} trunc
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%F = trunc <8 x i32> undef to <8 x i16>
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;CHECK: cost of 2 {{.*}} trunc
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;CHECK-AVX2: cost of 4 {{.*}} trunc
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;CHECK-AVX: cost of 4 {{.*}} trunc
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%F1 = trunc <16 x i16> undef to <16 x i8>
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;CHECK-AVX2: cost of 2 {{.*}} trunc
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;CHECK-AVX: cost of 4 {{.*}} trunc
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%F2 = trunc <8 x i32> undef to <8 x i8>
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;CHECK-AVX2: cost of 2 {{.*}} trunc
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;CHECK-AVX: cost of 4 {{.*}} trunc
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%F3 = trunc <4 x i64> undef to <4 x i8>
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;CHECK: cost of 3 {{.*}} trunc
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;CHECK-AVX2: cost of 4 {{.*}} trunc
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;CHECK-AVX: cost of 9 {{.*}} trunc
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%G = trunc <8 x i64> undef to <8 x i32>
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ret i32 undef
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}
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define i32 @masks8(<8 x i1> %in) {
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;CHECK: cost of 6 {{.*}} zext
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; CHECK-AVX2-LABEL: for function 'masks8'
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; CHECK-AVX-LABEL: for function 'masks8'
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;CHECK-AVX2: cost of 3 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%Z = zext <8 x i1> %in to <8 x i32>
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;CHECK: cost of 9 {{.*}} sext
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;CHECK-AVX2: cost of 3 {{.*}} sext
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;CHECK-AVX: cost of 7 {{.*}} sext
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%S = sext <8 x i1> %in to <8 x i32>
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ret i32 undef
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}
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define i32 @masks4(<4 x i1> %in) {
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;CHECK: cost of 8 {{.*}} sext
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; CHECK-AVX2-LABEL: for function 'masks4'
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; CHECK-AVX-LABEL: for function 'masks4'
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;CHECK-AVX2: cost of 3 {{.*}} zext
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;CHECK-AVX: cost of 4 {{.*}} zext
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%Z = zext <4 x i1> %in to <4 x i64>
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;CHECK-AVX2: cost of 3 {{.*}} sext
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;CHECK-AVX: cost of 6 {{.*}} sext
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%S = sext <4 x i1> %in to <4 x i64>
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ret i32 undef
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}
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define void @sitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) {
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; CHECK-LABEL: for function 'sitofp4'
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; CHECK: cost of 3 {{.*}} sitofp
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%A1 = sitofp <4 x i1> %a to <4 x float>
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; CHECK: cost of 3 {{.*}} sitofp
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@ -107,6 +157,7 @@ define void @sitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) {
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}
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define void @sitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) {
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; CHECK-LABEL: for function 'sitofp8'
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; CHECK: cost of 8 {{.*}} sitofp
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%A1 = sitofp <8 x i1> %a to <8 x float>
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@ -122,6 +173,7 @@ define void @sitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) {
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}
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define void @uitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) {
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; CHECK-LABEL: for function 'uitofp4'
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; CHECK: cost of 7 {{.*}} uitofp
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%A1 = uitofp <4 x i1> %a to <4 x float>
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; CHECK: cost of 7 {{.*}} uitofp
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@ -145,6 +197,7 @@ define void @uitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) {
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}
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define void @uitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) {
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; CHECK-LABEL: for function 'uitofp8'
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; CHECK: cost of 6 {{.*}} uitofp
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%A1 = uitofp <8 x i1> %a to <8 x float>
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