From f0d25117c60b428ade51d2ae266a9745b46dabbc Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Thu, 22 Dec 2011 19:55:21 +0000
Subject: [PATCH] ARM VFP add encoding of the bitcount to
 fixed-point<-->floating point. insns.

The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

llvm-svn: 147170
---
 llvm/lib/Target/ARM/ARMInstrFormats.td | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 80f377396c78..4b50e3bcca9e 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -1594,8 +1594,11 @@ class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
                 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
                 list<dag> pattern>
   : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
+  bits<5> fbits;
   // size (fixed-point number): sx == 0 ? 16 : 32
   let Inst{7} = op5; // sx
+  let Inst{5} = fbits{0};
+  let Inst{3-0} = fbits{4-1};
 }
 
 // VFP conversion instructions, if no NEON