forked from OSchip/llvm-project
parent
5b013f5050
commit
f0cfb83bb4
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@ -718,7 +718,7 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
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// indicate the scheduled cycle.
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SU->setHeightToAtLeast(CurCycle);
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// Reserve resources for the scheduled intruction.
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// Reserve resources for the scheduled instruction.
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EmitNode(SU);
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Sequence.push_back(SU);
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@ -170,7 +170,7 @@ private:
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/// slots to use the joint slots.
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void remapInstructions(DenseMap<int, int> &SlotRemap);
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/// The input program may contain intructions which are not inside lifetime
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/// The input program may contain instructions which are not inside lifetime
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/// markers. This can happen due to a bug in the compiler or due to a bug in
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/// user code (for example, returning a reference to a local variable).
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/// This procedure checks all of the instructions in the function and
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@ -36,7 +36,7 @@ bool NVPTXSplitBBatBar::runOnFunction(Function &F) {
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BasicBlock::iterator II = IB;
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BasicBlock::iterator IE = BI->end();
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// Skit the first intruction. No splitting is needed at this
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// Skit the first instruction. No splitting is needed at this
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// point even if this is a bar.
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while (II != IE) {
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if (IntrinsicInst *inst = dyn_cast<IntrinsicInst>(II)) {
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@ -9442,7 +9442,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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unsigned NumOperands = 0;
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// Truncate operations may prevent the merge of the SETCC instruction
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// and the arithmetic intruction before it. Attempt to truncate the operands
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// and the arithmetic instruction before it. Attempt to truncate the operands
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// of the arithmetic instruction and use a reduced bit-width instruction.
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bool NeedTruncation = false;
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SDValue ArithOp = Op;
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@ -11319,7 +11319,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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case Intrinsic::x86_avx2_permd:
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case Intrinsic::x86_avx2_permps:
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// Operands intentionally swapped. Mask is last operand to intrinsic,
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// but second operand for node/intruction.
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// but second operand for node/instruction.
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return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
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Op.getOperand(2), Op.getOperand(1));
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@ -29,7 +29,7 @@
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using namespace llvm;
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STATISTIC(IfHandled, "Number of 'expect' intrinsic intructions handled");
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STATISTIC(IfHandled, "Number of 'expect' intrinsic instructions handled");
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static cl::opt<uint32_t>
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LikelyBranchWeight("likely-branch-weight", cl::Hidden, cl::init(64),
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@ -533,7 +533,7 @@ namespace {
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default: break;
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case Instruction::GetElementPtr:
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// We mark this instruction as zero-cost because scalar GEPs are usually
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// lowered to the intruction addressing mode. At the moment we don't
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// lowered to the instruction addressing mode. At the moment we don't
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// generate vector GEPs.
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return 0;
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case Instruction::Br:
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@ -5,7 +5,7 @@
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Altivec does not provides an sext intruction, so it expands
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; Altivec does not provides an sext instruction, so it expands
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; a set of vector stores (stvx), bytes load/sign expand/store
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; (lbz/stb), and a final vector load (lvx) to load the result
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; extended vector.
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@ -40,7 +40,7 @@ entry:
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; CHECK: pop
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; CHECK: pop
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; Do not convert into single stream code. BranchProbability Analysis assumes
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; that branches which goes to "ret" intruction have lower probabilities.
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; that branches which goes to "ret" instruction have lower probabilities.
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switch i32 undef, label %bb7 [
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i32 37, label %bb43
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i32 48, label %bb5
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@ -183,7 +183,7 @@
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# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
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# -------------------------------------------------------------------------------------------------
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# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
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# The instruction is UNPREDICTABLE, and is not a valid intruction.
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# The instruction is UNPREDICTABLE, and is not a valid instruction.
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#
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# See also
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# A8.6.88 LSL (immediate)
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@ -201,7 +201,7 @@
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# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
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# -------------------------------------------------------------------------------------------------
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# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
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# The instruction is UNPREDICTABLE, and is not a valid intruction.
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# The instruction is UNPREDICTABLE, and is not a valid instruction.
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#
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# See also
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# A8.6.97 MOV (register)
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