forked from OSchip/llvm-project
parent
951ed1bdd2
commit
f0c955b4dc
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@ -107,10 +107,33 @@ bool isSubRegisterClass(const CodeGenRegisterClass &RC,
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return true;
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}
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static void addSubReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*> > &SubRegs,
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std::map<Record*, std::set<Record*> > &Aliases,
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RegisterInfoEmitter &RIE) {
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static void addSuperReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*> > &SubRegs,
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std::map<Record*, std::set<Record*> > &SuperRegs,
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std::map<Record*, std::set<Record*> > &Aliases,
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RegisterInfoEmitter &RIE) {
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if (R == S) {
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cerr << "Error: recursive sub-register relationship between"
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<< " register " << RIE.getQualifiedName(R)
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<< " and its sub-registers?\n";
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abort();
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}
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if (!SuperRegs[R].insert(S).second)
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return;
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SubRegs[S].insert(R);
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Aliases[R].insert(S);
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Aliases[S].insert(R);
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if (SuperRegs.count(S))
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for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
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E = SuperRegs[S].end(); I != E; ++I)
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addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
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}
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static void addSubSuperReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*> > &SubRegs,
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std::map<Record*, std::set<Record*> > &SuperRegs,
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std::map<Record*, std::set<Record*> > &Aliases,
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RegisterInfoEmitter &RIE) {
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if (R == S) {
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cerr << "Error: recursive sub-register relationship between"
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<< " register " << RIE.getQualifiedName(R)
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@ -120,12 +143,13 @@ static void addSubReg(Record *R, Record *S,
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if (!SubRegs[R].insert(S).second)
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return;
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addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
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Aliases[R].insert(S);
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Aliases[S].insert(R);
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if (SubRegs.count(S))
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for (std::set<Record*>::iterator I = SubRegs[S].begin(),
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E = SubRegs[S].end(); I != E; ++I)
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addSubReg(R, *I, SubRegs, Aliases, RIE);
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addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
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}
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// RegisterInfoEmitter::run - Main register file description emitter.
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@ -294,8 +318,9 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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<< "RegClass,\n";
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OS << " };\n";
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// Emit register sub-registers / aliases...
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// Emit register sub-registers / super-registers, aliases...
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std::map<Record*, std::set<Record*> > RegisterSubRegs;
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std::map<Record*, std::set<Record*> > RegisterSuperRegs;
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std::map<Record*, std::set<Record*> > RegisterAliases;
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const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
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@ -320,6 +345,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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}
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}
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// Process sub-register sets.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *R = Regs[i].TheDef;
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std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
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@ -330,7 +356,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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cerr << "Warning: register " << getQualifiedName(SubReg)
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<< " specified as a sub-register of " << getQualifiedName(R)
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<< " multiple times!\n";
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addSubReg(R, SubReg, RegisterSubRegs, RegisterAliases, *this);
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addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
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RegisterAliases, *this);
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}
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}
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@ -365,9 +392,25 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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OS << getQualifiedName(*ASI) << ", ";
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OS << "0 };\n";
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}
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OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
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OS << " { \"NOREG\",\t0,\t0 },\n";
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if (!RegisterSuperRegs.empty())
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OS << "\n\n // Register Super-registers Sets...\n";
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// Emit the empty super-registers list
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OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
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// Loop over all of the registers which have super-registers, emitting the
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// super-registers list to memory.
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for (std::map<Record*, std::set<Record*> >::iterator
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I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
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OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
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for (std::set<Record*>::iterator ASI = I->second.begin(),
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E = I->second.end(); ASI != E; ++ASI)
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OS << getQualifiedName(*ASI) << ", ";
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OS << "0 };\n";
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}
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OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
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OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
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// Now that register alias and sub-registers sets have been emitted, emit the
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// register descriptors now.
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@ -385,9 +428,13 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
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else
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OS << "Empty_AliasSet,\t";
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if (RegisterSubRegs.count(Reg.TheDef))
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OS << Reg.getName() << "_SubRegsSet },\n";
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OS << Reg.getName() << "_SubRegsSet,\t";
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else
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OS << "Empty_SubRegsSet },\n";
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OS << "Empty_SubRegsSet,\t";
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if (RegisterSuperRegs.count(Reg.TheDef))
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OS << Reg.getName() << "_SuperRegsSet },\n";
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else
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OS << "Empty_SuperRegsSet },\n";
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}
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OS << " };\n"; // End of register descriptors...
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OS << "}\n\n"; // End of anonymous namespace...
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