forked from OSchip/llvm-project
Match a pattern generated by a dag combiner opt where:
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1)) Thanks to Akira for pointing that. llvm-svn: 121163
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@ -271,12 +271,16 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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switch(MO.getTargetFlags()) {
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case MipsII::MO_GPREL: O << "%gp_rel("; break;
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case MipsII::MO_GOT_CALL: O << "%call16("; break;
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case MipsII::MO_GOT:
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if (MI->getOpcode() == Mips::LW)
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case MipsII::MO_GOT: {
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const MachineOperand &LastMO = MI->getOperand(opNum-1);
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bool LastMOIsGP = LastMO.getType() == MachineOperand::MO_Register
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&& LastMO.getReg() == Mips::GP;
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if (MI->getOpcode() == Mips::LW || LastMOIsGP)
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O << "%got(";
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else
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O << "%lo(";
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break;
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}
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case MipsII::MO_ABS_HILO:
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if (MI->getOpcode() == Mips::LUi)
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O << "%hi(";
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@ -597,6 +597,12 @@ def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
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(MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
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// select patterns with got access
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def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs),
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(i32 tglobaladdr:$T), CPURegs:$F),
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(MOVN CPURegs:$F, (ADDiu GP, tglobaladdr:$T),
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(XOR CPURegs:$lhs, CPURegs:$rhs))>;
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// setcc patterns
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def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
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(SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
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@ -0,0 +1,15 @@
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; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
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@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
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@i3 = common global i32* null, align 4
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; CHECK: lw $3, %got(i3)($gp)
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; CHECK: addiu $5, $gp, %got(i1)
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define i32* @cmov1(i32 %s) nounwind readonly {
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entry:
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%tobool = icmp ne i32 %s, 0
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%tmp1 = load i32** @i3, align 4
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%cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
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ret i32* %cond
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}
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