maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86InstPrinter] Introduce markup tags emission 

x86 assembly syntax emission now leverages markup tags, if enabled.

Differential Revision: https://reviews.llvm.org/D129869
This commit is contained in:
Antonio Frighetto 2022-09-01 21:04:34 -07:00 committed by Fangrui Song
parent 4e99079774
commit f0c50447f6
3 changed files with 23 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
View File

@ -320,6 +320,7 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
O << markup("<imm:");
if (PrintBranchImmAsAddress) {
uint64_t Target = Address + Op.getImm();
if (MAI.getCodePointerSize() == 4)
@ -327,6 +328,7 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
O << formatHex(Target);
} else
O << formatImm(Op.getImm());
O << markup(">");
} else {
assert(Op.isExpr() && "unknown pcrel immediate operand");
// If a symbolic branch target was added as a constant expression then print
@ -334,7 +336,7 @@ void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
int64_t Address;
if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
O << formatHex((uint64_t)Address);
O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
} else {
// Otherwise, just print the expression.
Op.getExpr()->print(O, &MAI);

27
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
View File

@ -34,7 +34,7 @@ using namespace llvm;
#include "X86GenAsmWriter1.inc"
void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
}
void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
@ -361,7 +361,7 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (Op.isReg()) {
printRegName(O, Op.getReg());
} else if (Op.isImm()) {
O << formatImm((int64_t)Op.getImm());
O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
} else {
assert(Op.isExpr() && "unknown operand kind in printOperand");
O << "offset ";
@ -388,7 +388,7 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
O << '[';
O << markup("<mem:") << '[';
bool NeedPlus = false;
if (BaseReg.getReg()) {
@ -419,28 +419,28 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
DispVal = -DispVal;
}
}
O << formatImm(DispVal);
O << markup("<imm:") << formatImm(DispVal) << markup(">");
}
}
O << ']';
O << ']' << markup(">");
}
void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
O << '[';
O << markup("<mem:") << '[';
printOperand(MI, Op, O);
O << ']';
O << ']' << markup(">");
}
void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
raw_ostream &O) {
// DI accesses are always ES-based.
O << "es:[";
O << "es:" << markup("<mem:") << '[';
printOperand(MI, Op, O);
O << ']';
O << ']' << markup(">");
}
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
@ -450,16 +450,16 @@ void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
// If this has a segment register, print it.
printOptionalSegReg(MI, Op + 1, O);
O << '[';
O << markup("<mem:") << '[';
if (DispSpec.isImm()) {
O << formatImm(DispSpec.getImm());
O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
} else {
assert(DispSpec.isExpr() && "non-immediate displacement?");
DispSpec.getExpr()->print(O, &MAI);
}
O << ']';
O << ']' << markup(">");
}
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
@ -467,7 +467,8 @@ void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
if (MI->getOperand(Op).isExpr())
return MI->getOperand(Op).getExpr()->print(O, &MAI);
O << formatImm(MI->getOperand(Op).getImm() & 0xff);
O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
<< markup(">");
}
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,

6
llvm/test/MC/Disassembler/X86/marked-up-32.txt Normal file
View File

@ -0,0 +1,6 @@
# RUN: llvm-mc -triple=i386 --mdis %s | FileCheck %s
# CHECK: je <imm:60>
0x0f 0x84 0x3c 0x00 0x00 0x00
# CHECK: jecxz <imm:-127>
0xe3 0x81