forked from OSchip/llvm-project
[WebAssembly] Implement ReverseBranchCondition, and re-enable MachineBlockPlacement
This patch introduces a codegen-only instruction currently named br_unless, which makes it convenient to implement ReverseBranchCondition and re-enable the MachineBlockPlacement pass. Then in a late pass, it lowers br_unless back into br_if. Differential Revision: http://reviews.llvm.org/D14995 llvm-svn: 254826
This commit is contained in:
Dan Gohman
parent
064a672f65
commit
f0b165a7f8
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@ -18,6 +18,7 @@ add_llvm_target(WebAssemblyCodeGen
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WebAssemblyISelDAGToDAG.cpp
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WebAssemblyISelLowering.cpp
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WebAssemblyInstrInfo.cpp
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WebAssemblyLowerBrUnless.cpp
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WebAssemblyMachineFunctionInfo.cpp
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WebAssemblyMCInstLower.cpp
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WebAssemblyOptimizeReturned.cpp
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@ -32,6 +32,7 @@ FunctionPass *createWebAssemblyStoreResults();
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FunctionPass *createWebAssemblyRegStackify();
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FunctionPass *createWebAssemblyRegColoring();
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FunctionPass *createWebAssemblyCFGStackify();
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FunctionPass *createWebAssemblyLowerBrUnless();
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FunctionPass *createWebAssemblyRegNumbering();
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FunctionPass *createWebAssemblyPeephole();
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@ -15,9 +15,13 @@
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let Defs = [ARGUMENTS] in {
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
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def BR_IF : I<(outs), (ins I32:$a, bb_op:$dst),
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[(brcond I32:$a, bb:$dst)],
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"br_if \t$a, $dst">;
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// The condition operand is a boolean value which WebAssembly represents as i32.
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def BR_IF : I<(outs), (ins I32:$cond, bb_op:$dst),
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[(brcond I32:$cond, bb:$dst)],
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"br_if \t$cond, $dst">;
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let isCodeGenOnly = 1 in
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def BR_UNLESS : I<(outs), (ins I32:$cond, bb_op:$dst), [],
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"br_unless\t$cond, $dst">;
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let isBarrier = 1 in {
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def BR : I<(outs), (ins bb_op:$dst),
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[(br bb:$dst)],
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@ -25,6 +29,15 @@ def BR : I<(outs), (ins bb_op:$dst),
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} // isBarrier = 1
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} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
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} // Defs = [ARGUMENTS]
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def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
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(BR_IF I32:$cond, bb_op:$dst)>;
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def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
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(BR_UNLESS I32:$cond, bb_op:$dst)>;
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let Defs = [ARGUMENTS] in {
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// TODO: SelectionDAG's lowering insists on using a pointer as the index for
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// jump tables, so in practice we don't ever use TABLESWITCH_I64 in wasm32 mode
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// currently.
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@ -71,6 +71,15 @@ bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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case WebAssembly::BR_IF:
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if (HaveCond)
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return true;
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Cond.push_back(MachineOperand::CreateImm(true));
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Cond.push_back(MI.getOperand(0));
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TBB = MI.getOperand(1).getMBB();
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HaveCond = true;
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break;
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case WebAssembly::BR_UNLESS:
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if (HaveCond)
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return true;
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Cond.push_back(MachineOperand::CreateImm(false));
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Cond.push_back(MI.getOperand(0));
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TBB = MI.getOperand(1).getMBB();
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HaveCond = true;
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@ -113,8 +122,6 @@ unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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assert(Cond.size() <= 1);
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if (Cond.empty()) {
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if (!TBB)
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return 0;
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@ -123,7 +130,17 @@ unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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return 1;
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}
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BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addOperand(Cond[0]).addMBB(TBB);
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assert(Cond.size() == 2 && "Expected a flag and a successor block");
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if (Cond[0].getImm()) {
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BuildMI(&MBB, DL, get(WebAssembly::BR_IF))
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.addOperand(Cond[1])
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.addMBB(TBB);
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} else {
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BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
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.addOperand(Cond[1])
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.addMBB(TBB);
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}
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if (!FBB)
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return 1;
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@ -133,10 +150,7 @@ unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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bool WebAssemblyInstrInfo::ReverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1);
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// TODO: Add branch reversal here... And re-enable MachineBlockPlacementID
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// when we do.
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return true;
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assert(Cond.size() == 2 && "Expected a flag and a successor block");
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Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
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return false;
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}
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@ -0,0 +1,133 @@
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//===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file lowers br_unless into br_if with an inverted condition.
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///
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/// br_unless is not currently in the spec, but it's very convenient for LLVM
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/// to use. This pass allows LLVM to use it, for now.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-lower-br_unless"
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namespace {
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class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
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const char *getPassName() const override {
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return "WebAssembly Lower br_unless";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyLowerBrUnless::ID = 0;
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FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
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return new WebAssemblyLowerBrUnless();
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}
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bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** Lowering br_unless **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
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const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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auto &MRI = MF.getRegInfo();
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for (auto &MBB : MF) {
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for (auto MII = MBB.begin(); MII != MBB.end(); ) {
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MachineInstr *MI = &*MII++;
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if (MI->getOpcode() != WebAssembly::BR_UNLESS)
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continue;
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unsigned Cond = MI->getOperand(0).getReg();
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bool Inverted = false;
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// Attempt to invert the condition in place.
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if (MFI.isVRegStackified(Cond)) {
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assert(MRI.hasOneDef(Cond));
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MachineInstr *Def = MRI.getVRegDef(Cond);
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switch (Def->getOpcode()) {
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using namespace WebAssembly;
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case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
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case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
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case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
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case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
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case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
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case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
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case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
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case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break;
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case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break;
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case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted = true; break;
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case EQ_I64: Def->setDesc(TII.get(NE_I64)); Inverted = true; break;
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case NE_I64: Def->setDesc(TII.get(EQ_I64)); Inverted = true; break;
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case GT_S_I64: Def->setDesc(TII.get(LE_S_I64)); Inverted = true; break;
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case GE_S_I64: Def->setDesc(TII.get(LT_S_I64)); Inverted = true; break;
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case LT_S_I64: Def->setDesc(TII.get(GE_S_I64)); Inverted = true; break;
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case LE_S_I64: Def->setDesc(TII.get(GT_S_I64)); Inverted = true; break;
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case GT_U_I64: Def->setDesc(TII.get(LE_U_I64)); Inverted = true; break;
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case GE_U_I64: Def->setDesc(TII.get(LT_U_I64)); Inverted = true; break;
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case LT_U_I64: Def->setDesc(TII.get(GE_U_I64)); Inverted = true; break;
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case LE_U_I64: Def->setDesc(TII.get(GT_U_I64)); Inverted = true; break;
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case EQ_F32: Def->setDesc(TII.get(NE_F32)); Inverted = true; break;
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case NE_F32: Def->setDesc(TII.get(EQ_F32)); Inverted = true; break;
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case EQ_F64: Def->setDesc(TII.get(NE_F64)); Inverted = true; break;
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case NE_F64: Def->setDesc(TII.get(EQ_F64)); Inverted = true; break;
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default: break;
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}
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}
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// If we weren't able to invert the condition in place. Insert an
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// expression to invert it.
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if (!Inverted) {
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unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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MFI.stackifyVReg(ZeroReg);
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BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), ZeroReg)
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.addImm(0);
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unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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MFI.stackifyVReg(Tmp);
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BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQ_I32), Tmp)
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.addReg(Cond)
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.addReg(ZeroReg);
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Cond = Tmp;
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Inverted = true;
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}
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// The br_unless condition has now been inverted. Insert a br_if and
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// delete the br_unless.
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assert(Inverted);
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BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
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.addReg(Cond)
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.addMBB(MI->getOperand(1).getMBB());
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MBB.erase(MI);
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}
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}
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return true;
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}
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@ -64,7 +64,7 @@ bool WebAssemblyPeephole::runOnMachineFunction(MachineFunction &MF) {
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// can use $discard instead.
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MachineOperand &MO = MI.getOperand(0);
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unsigned OldReg = MO.getReg();
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if (OldReg == MI.getOperand(2).getReg()) {
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if (OldReg == MI.getOperand(3).getReg()) {
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unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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MO.setReg(NewReg);
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MO.setIsDead();
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@ -171,10 +171,6 @@ void WebAssemblyPassConfig::addPostRegAlloc() {
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// Fails with: should be run after register allocation.
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disablePass(&MachineCopyPropagationID);
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// TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement
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// can create ugly-looking control flow.
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disablePass(&MachineBlockPlacementID);
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// Run the register coloring pass to reduce the total number of registers.
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addPass(createWebAssemblyRegColoring());
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}
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@ -183,6 +179,9 @@ void WebAssemblyPassConfig::addPreEmitPass() {
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// Put the CFG in structured form; insert BLOCK and LOOP markers.
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addPass(createWebAssemblyCFGStackify());
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// Lower br_unless into br_if.
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addPass(createWebAssemblyLowerBrUnless());
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// Create a mapping from LLVM CodeGen virtual registers to wasm registers.
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addPass(createWebAssemblyRegNumbering());
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@ -1,4 +1,5 @@
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; RUN: llc < %s -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -asm-verbose=false -disable-block-placement | FileCheck %s
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; RUN: llc < %s -asm-verbose=false | FileCheck -check-prefix=OPT %s
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; Test the CFG stackifier pass.
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@ -12,10 +13,21 @@ declare void @something()
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; CHECK-LABEL: test0:
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; CHECK: loop
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; CHECK: i32.add
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; CHECK-NOT: br
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; CHECK: br_if
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; CHECK-NOT: br
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; CHECK: call
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; CHECK: br BB0_1{{$}}
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; CHECK: return{{$}}
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; OPT-LABEL: test0:
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; OPT: loop
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; OPT: i32.add
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; OPT-NOT: br
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; OPT: br_if
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; OPT-NOT: br
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; OPT: call
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; OPT: br BB0_1{{$}}
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; OPT: return{{$}}
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define void @test0(i32 %n) {
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entry:
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br label %header
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@ -40,10 +52,21 @@ back:
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; CHECK-LABEL: test1:
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; CHECK: loop
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; CHECK: i32.add
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; CHECK-NOT: br
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; CHECK: br_if
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; CHECK-NOT: br
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; CHECK: call
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; CHECK: br BB1_1{{$}}
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; CHECK: return{{$}}
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; OPT-LABEL: test1:
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; OPT: loop
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; OPT: i32.add
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; OPT-NOT: br
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; OPT: br_if
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; OPT-NOT: br
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; OPT: call
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; OPT: br BB1_1{{$}}
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; OPT: return{{$}}
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define void @test1(i32 %n) {
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entry:
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br label %header
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@ -69,9 +92,16 @@ back:
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; CHECK: block BB2_2{{$}}
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; CHECK: br_if {{.*}}, BB2_2{{$}}
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; CHECK: BB2_1:
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; CHECK: br_if $pop{{[0-9]+}}, BB2_1{{$}}
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; CHECK: br_if ${{[0-9]+}}, BB2_1{{$}}
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; CHECK: BB2_2:
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; CHECK: return{{$}}
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; OPT-LABEL: test2:
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; OPT: block BB2_2{{$}}
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; OPT: br_if {{.*}}, BB2_2{{$}}
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; OPT: BB2_1:
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; OPT: br_if ${{[0-9]+}}, BB2_1{{$}}
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; OPT: BB2_2:
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; OPT: return{{$}}
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define void @test2(double* nocapture %p, i32 %n) {
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entry:
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%cmp.4 = icmp sgt i32 %n, 0
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@ -100,13 +130,23 @@ for.end:
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; CHECK-LABEL: doublediamond:
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; CHECK: block BB3_5{{$}}
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; CHECK: block BB3_2{{$}}
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; CHECK: br_if $pop{{[0-9]+}}, BB3_2{{$}}
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; CHECK: br_if $0, BB3_2{{$}}
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; CHECK: block BB3_4{{$}}
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; CHECK: br_if $pop{{[0-9]+}}, BB3_4{{$}}
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; CHECK: br_if $1, BB3_4{{$}}
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; CHECK: br BB3_5{{$}}
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; CHECK: BB3_4:
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; CHECK: BB3_5:
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; CHECK: return ${{[0-9]+}}{{$}}
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; OPT-LABEL: doublediamond:
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; OPT: block BB3_5{{$}}
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; OPT: block BB3_4{{$}}
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; OPT: br_if {{.*}}, BB3_4{{$}}
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; OPT: block BB3_3{{$}}
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; OPT: br_if {{.*}}, BB3_3{{$}}
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; OPT: br BB3_5{{$}}
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; OPT: BB3_4:
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; OPT: BB3_5:
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; OPT: return ${{[0-9]+}}{{$}}
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define i32 @doublediamond(i32 %a, i32 %b, i32* %p) {
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entry:
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%c = icmp eq i32 %a, 0
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@ -132,9 +172,14 @@ exit:
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; CHECK-LABEL: triangle:
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; CHECK: block BB4_2{{$}}
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; CHECK: br_if $pop{{[0-9]+}}, BB4_2{{$}}
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; CHECK: br_if $1, BB4_2{{$}}
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; CHECK: BB4_2:
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; CHECK: return ${{[0-9]+}}{{$}}
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; OPT-LABEL: triangle:
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; OPT: block BB4_2{{$}}
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; OPT: br_if $1, BB4_2{{$}}
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; OPT: BB4_2:
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; OPT: return ${{[0-9]+}}{{$}}
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define i32 @triangle(i32* %p, i32 %a) {
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entry:
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%c = icmp eq i32 %a, 0
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@ -151,11 +196,19 @@ exit:
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; CHECK-LABEL: diamond:
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; CHECK: block BB5_3{{$}}
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; CHECK: block BB5_2{{$}}
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; CHECK: br_if $pop{{[0-9]+}}, BB5_2{{$}}
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; CHECK: br_if $1, BB5_2{{$}}
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; CHECK: br BB5_3{{$}}
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; CHECK: BB5_2:
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; CHECK: BB5_3:
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; CHECK: return ${{[0-9]+}}{{$}}
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; OPT-LABEL: diamond:
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; OPT: block BB5_3{{$}}
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; OPT: block BB5_2{{$}}
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; OPT: br_if {{.*}}, BB5_2{{$}}
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; OPT: br BB5_3{{$}}
|
||||
; OPT: BB5_2:
|
||||
; OPT: BB5_3:
|
||||
; OPT: return ${{[0-9]+}}{{$}}
|
||||
define i32 @diamond(i32* %p, i32 %a) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
|
|
@ -175,6 +228,9 @@ exit:
|
|||
; CHECK-LABEL: single_block:
|
||||
; CHECK-NOT: br
|
||||
; CHECK: return $pop{{[0-9]+}}{{$}}
|
||||
; OPT-LABEL: single_block:
|
||||
; OPT-NOT: br
|
||||
; OPT: return $pop{{[0-9]+}}{{$}}
|
||||
define i32 @single_block(i32* %p) {
|
||||
entry:
|
||||
store volatile i32 0, i32* %p
|
||||
|
|
@ -187,6 +243,12 @@ entry:
|
|||
; CHECK: i32.store $discard=, 0($0), $pop{{[0-9]+}}{{$}}
|
||||
; CHECK: br BB7_1{{$}}
|
||||
; CHECK: BB7_2:
|
||||
; OPT-LABEL: minimal_loop:
|
||||
; OPT-NOT: br
|
||||
; OPT: BB7_1:
|
||||
; OPT: i32.store $discard=, 0($0), $pop{{[0-9]+}}{{$}}
|
||||
; OPT: br BB7_1{{$}}
|
||||
; OPT: BB7_2:
|
||||
define i32 @minimal_loop(i32* %p) {
|
||||
entry:
|
||||
store volatile i32 0, i32* %p
|
||||
|
|
@ -203,6 +265,13 @@ loop:
|
|||
; CHECK: br_if $pop{{[0-9]+}}, BB8_1{{$}}
|
||||
; CHECK: BB8_2:
|
||||
; CHECK: return ${{[0-9]+}}{{$}}
|
||||
; OPT-LABEL: simple_loop:
|
||||
; OPT-NOT: br
|
||||
; OPT: BB8_1:
|
||||
; OPT: loop BB8_2{{$}}
|
||||
; OPT: br_if {{.*}}, BB8_1{{$}}
|
||||
; OPT: BB8_2:
|
||||
; OPT: return ${{[0-9]+}}{{$}}
|
||||
define i32 @simple_loop(i32* %p, i32 %a) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
|
|
@ -218,12 +287,20 @@ exit:
|
|||
|
||||
; CHECK-LABEL: doubletriangle:
|
||||
; CHECK: block BB9_4{{$}}
|
||||
; CHECK: br_if $pop{{[0-9]+}}, BB9_4{{$}}
|
||||
; CHECK: br_if $0, BB9_4{{$}}
|
||||
; CHECK: block BB9_3{{$}}
|
||||
; CHECK: br_if $pop{{[0-9]+}}, BB9_3{{$}}
|
||||
; CHECK: br_if $1, BB9_3{{$}}
|
||||
; CHECK: BB9_3:
|
||||
; CHECK: BB9_4:
|
||||
; CHECK: return ${{[0-9]+}}{{$}}
|
||||
; OPT-LABEL: doubletriangle:
|
||||
; OPT: block BB9_4{{$}}
|
||||
; OPT: br_if $0, BB9_4{{$}}
|
||||
; OPT: block BB9_3{{$}}
|
||||
; OPT: br_if $1, BB9_3{{$}}
|
||||
; OPT: BB9_3:
|
||||
; OPT: BB9_4:
|
||||
; OPT: return ${{[0-9]+}}{{$}}
|
||||
define i32 @doubletriangle(i32 %a, i32 %b, i32* %p) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
|
|
@ -247,12 +324,21 @@ exit:
|
|||
; CHECK-LABEL: ifelse_earlyexits:
|
||||
; CHECK: block BB10_4{{$}}
|
||||
; CHECK: block BB10_2{{$}}
|
||||
; CHECK: br_if $pop{{[0-9]+}}, BB10_2{{$}}
|
||||
; CHECK: br_if $0, BB10_2{{$}}
|
||||
; CHECK: br BB10_4{{$}}
|
||||
; CHECK: BB10_2:
|
||||
; CHECK: br_if $pop{{[0-9]+}}, BB10_4{{$}}
|
||||
; CHECK: br_if $1, BB10_4{{$}}
|
||||
; CHECK: BB10_4:
|
||||
; CHECK: return ${{[0-9]+}}{{$}}
|
||||
; OPT-LABEL: ifelse_earlyexits:
|
||||
; OPT: block BB10_4{{$}}
|
||||
; OPT: block BB10_3{{$}}
|
||||
; OPT: br_if {{.*}}, BB10_3{{$}}
|
||||
; OPT: br_if $1, BB10_4{{$}}
|
||||
; OPT: br BB10_4{{$}}
|
||||
; OPT: BB10_3:
|
||||
; OPT: BB10_4:
|
||||
; OPT: return ${{[0-9]+}}{{$}}
|
||||
define i32 @ifelse_earlyexits(i32 %a, i32 %b, i32* %p) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
|
|
@ -278,16 +364,31 @@ exit:
|
|||
; CHECK: loop BB11_7{{$}}
|
||||
; CHECK: block BB11_6{{$}}
|
||||
; CHECK: block BB11_3{{$}}
|
||||
; CHECK: br_if $pop{{.*}}, BB11_3{{$}}
|
||||
; CHECK: br_if $0, BB11_3{{$}}
|
||||
; CHECK: br BB11_6{{$}}
|
||||
; CHECK: BB11_3:
|
||||
; CHECK: block BB11_5{{$}}
|
||||
; CHECK: br_if $pop{{.*}}, BB11_5{{$}}
|
||||
; CHECK: br_if $1, BB11_5{{$}}
|
||||
; CHECK: br BB11_6{{$}}
|
||||
; CHECK: BB11_5:
|
||||
; CHECK: BB11_6:
|
||||
; CHECK: br BB11_1{{$}}
|
||||
; CHECK: BB11_7:
|
||||
; OPT-LABEL: doublediamond_in_a_loop:
|
||||
; OPT: BB11_1:
|
||||
; OPT: loop BB11_7{{$}}
|
||||
; OPT: block BB11_6{{$}}
|
||||
; OPT: block BB11_5{{$}}
|
||||
; OPT: br_if {{.*}}, BB11_5{{$}}
|
||||
; OPT: block BB11_4{{$}}
|
||||
; OPT: br_if {{.*}}, BB11_4{{$}}
|
||||
; OPT: br BB11_6{{$}}
|
||||
; OPT: BB11_4:
|
||||
; OPT: br BB11_6{{$}}
|
||||
; OPT: BB11_5:
|
||||
; OPT: BB11_6:
|
||||
; OPT: br BB11_1{{$}}
|
||||
; OPT: BB11_7:
|
||||
define i32 @doublediamond_in_a_loop(i32 %a, i32 %b, i32* %p) {
|
||||
entry:
|
||||
br label %header
|
||||
|
|
|
|||
|
|
@ -50,22 +50,35 @@ define i32 @yes1(i32* %q) {
|
|||
; rearranged to make the stack contiguous.
|
||||
|
||||
; CHECK-LABEL: stack_uses:
|
||||
; CHECK-NEXT: .param i32{{$}}
|
||||
; CHECK-NEXT: .param i32, i32, i32, i32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: local i32, i32{{$}}
|
||||
; CHECK-NEXT: i32.const $1=, 1{{$}}
|
||||
; CHECK-NEXT: i32.const $2=, 0{{$}}
|
||||
; CHECK-NEXT: i32.and $push0=, $0, $1{{$}}
|
||||
; CHECK-NEXT: i32.eq $push1=, $pop0, $2{{$}}
|
||||
; CHECK-NEXT: block BB4_2{{$}}
|
||||
; CHECK-NEXT: br_if $pop1, BB4_2{{$}}
|
||||
; CHECK-NEXT: return $2{{$}}
|
||||
; CHECK-NEXT: BB4_2:{{$}}
|
||||
; CHECK-NEXT: return $1{{$}}
|
||||
define i32 @stack_uses(i32 %x) {
|
||||
; CHECK-NEXT: .local i32, i32{{$}}
|
||||
; CHECK-NEXT: i32.const $4=, 1{{$}}
|
||||
; CHECK-NEXT: i32.const $5=, 2{{$}}
|
||||
; CHECK-NEXT: i32.lt_s $push0=, $0, $4{{$}}
|
||||
; CHECK-NEXT: i32.lt_s $push1=, $1, $5{{$}}
|
||||
; CHECK-NEXT: i32.xor $push4=, $pop0, $pop1{{$}}
|
||||
; CHECK-NEXT: i32.lt_s $push2=, $2, $4{{$}}
|
||||
; CHECK-NEXT: i32.lt_s $push3=, $3, $5{{$}}
|
||||
; CHECK-NEXT: i32.xor $push5=, $pop2, $pop3{{$}}
|
||||
; CHECK-NEXT: i32.xor $push6=, $pop4, $pop5{{$}}
|
||||
; CHECK-NEXT: i32.ne $push7=, $pop6, $4{{$}}
|
||||
; CHECK-NEXT: block BB4_2{{$}}
|
||||
; CHECK-NEXT: br_if $pop7, BB4_2{{$}}
|
||||
; CHECK-NEXT: i32.const $push8=, 0{{$}}
|
||||
; CHECK-NEXT: return $pop8{{$}}
|
||||
; CHECK-NEXT: BB4_2:
|
||||
; CHECK-NEXT: return $4{{$}}
|
||||
define i32 @stack_uses(i32 %x, i32 %y, i32 %z, i32 %w) {
|
||||
entry:
|
||||
%c = trunc i32 %x to i1
|
||||
br i1 %c, label %true, label %false
|
||||
%c = icmp sle i32 %x, 0
|
||||
%d = icmp sle i32 %y, 1
|
||||
%e = icmp sle i32 %z, 0
|
||||
%f = icmp sle i32 %w, 1
|
||||
%g = xor i1 %c, %d
|
||||
%h = xor i1 %e, %f
|
||||
%i = xor i1 %g, %h
|
||||
br i1 %i, label %true, label %false
|
||||
true:
|
||||
ret i32 0
|
||||
false:
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
; RUN: llc < %s -asm-verbose=false | FileCheck %s
|
||||
; RUN: llc < %s -asm-verbose=false -disable-block-placement | FileCheck %s
|
||||
|
||||
; Test switch instructions.
|
||||
; Test switch instructions. Block placement is disabled because it reorders
|
||||
; the blocks in a way that isn't interesting here.
|
||||
|
||||
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
|
||||
target triple = "wasm32-unknown-unknown"
|
||||
|
|
|
|||
Loading…
Reference in New Issue