forked from OSchip/llvm-project
[AArch64][SVE] Replace fmul, fadd and fsub LLVM IR instrinsics with LLVM IR binary ops
Replacing fmul and fadd instrinsics with their binary ops results more succinct AArch64 SVE output, e.g.: 4: 65428041 fmul z1.h, p0/m, z1.h, z2.h 8: 65408020 fadd z0.h, p0/m, z0.h, z1.h -> 4: 65620020 fmla z0.h, p0/m, z1.h, z2.h
This commit is contained in:
Matthew Devereau
parent
c1d46d3461
commit
f085a9db8b
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@ -695,6 +695,33 @@ static Optional<Instruction *> instCombineSVEPTest(InstCombiner &IC,
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return None;
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}
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static Instruction::BinaryOps intrinsicIDToBinOpCode(unsigned Intrinsic) {
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switch (Intrinsic) {
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case Intrinsic::aarch64_sve_fmul:
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return Instruction::BinaryOps::FMul;
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case Intrinsic::aarch64_sve_fadd:
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return Instruction::BinaryOps::FAdd;
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case Intrinsic::aarch64_sve_fsub:
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return Instruction::BinaryOps::FSub;
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default:
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return Instruction::BinaryOpsEnd;
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}
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}
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static Optional<Instruction *> instCombineSVEVectorBinOp(InstCombiner &IC,
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IntrinsicInst &II) {
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auto BinOpCode = intrinsicIDToBinOpCode(II.getIntrinsicID());
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if (BinOpCode == Instruction::BinaryOpsEnd ||
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!match(II.getOperand(0),
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m_Intrinsic<Intrinsic::aarch64_sve_ptrue>(
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m_ConstantInt<AArch64SVEPredPattern::all>())))
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return None;
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IRBuilder<> Builder(II.getContext());
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Builder.SetInsertPoint(&II);
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return IC.replaceInstUsesWith(
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II, Builder.CreateBinOp(BinOpCode, II.getOperand(1), II.getOperand(2)));
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}
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static Optional<Instruction *> instCombineSVEVectorMul(InstCombiner &IC,
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IntrinsicInst &II) {
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auto *OpPredicate = II.getOperand(0);
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@ -744,7 +771,7 @@ static Optional<Instruction *> instCombineSVEVectorMul(InstCombiner &IC,
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}
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}
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return None;
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return instCombineSVEVectorBinOp(IC, II);
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}
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static Optional<Instruction *> instCombineSVEUnpack(InstCombiner &IC,
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@ -871,6 +898,9 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
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case Intrinsic::aarch64_sve_mul:
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case Intrinsic::aarch64_sve_fmul:
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return instCombineSVEVectorMul(IC, II);
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case Intrinsic::aarch64_sve_fadd:
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case Intrinsic::aarch64_sve_fsub:
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return instCombineSVEVectorBinOp(IC, II);
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case Intrinsic::aarch64_sve_tbl:
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return instCombineSVETBL(IC, II);
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case Intrinsic::aarch64_sve_uunpkhi:
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@ -0,0 +1,111 @@
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; RUN: opt -S -instcombine < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
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; SVE intrinsics fmul and fadd should be replaced with regular fmul and fadd
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declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fmul_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fmul_intrinsic_half
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; CHECK-NEXT: %1 = fmul <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fmul_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fmul_intrinsic_float
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; CHECK-NEXT: %1 = fmul <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fmul_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fmul_intrinsic_double
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; CHECK-NEXT: %1 = fmul <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fadd_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fadd_intrinsic_half
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; CHECK-NEXT: %1 = fadd <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fadd_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fadd_intrinsic_float
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; CHECK-NEXT: %1 = fadd <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fadd_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fadd_intrinsic_double
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; CHECK-NEXT: %1 = fadd <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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define <vscale x 8 x half> @replace_fsub_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_half
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; CHECK-NEXT: %1 = fsub <vscale x 8 x half> %a, %b
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; CHECK-NEXT: ret <vscale x 8 x half> %1
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %2
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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define <vscale x 4 x float> @replace_fsub_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_float
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; CHECK-NEXT: %1 = fsub <vscale x 4 x float> %a, %b
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; CHECK-NEXT: ret <vscale x 4 x float> %1
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %2
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}
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declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 2 x double> @replace_fsub_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @replace_fsub_intrinsic_double
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; CHECK-NEXT: %1 = fsub <vscale x 2 x double> %a, %b
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; CHECK-NEXT: ret <vscale x 2 x double> %1
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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define <vscale x 2 x double> @no_replace_on_non_ptrue_all(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
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; CHECK-LABEL: @no_replace_on_non_ptrue_all
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; CHECK-NEXT: %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)
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; CHECK-NEXT: %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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; CHECK-NEXT: ret <vscale x 2 x double> %2
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)
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%2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %2
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}
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attributes #0 = { "target-features"="+sve" }
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