forked from OSchip/llvm-project
Clean up a bunch of whitespace issues and fix a comment typo.
No functional changes. llvm-svn: 68808
This commit is contained in:
Bob Wilson
parent
e8b48b49c9
commit
f074ca7454
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@ -685,7 +685,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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// Perform the original store, only redirected to the stack slot.
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SDValue Store = DAG.getTruncStore(Chain, dl,
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Val, StackPtr, NULL, 0,StoredVT);
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Val, StackPtr, NULL, 0, StoredVT);
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SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
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SmallVector<SDValue, 8> Stores;
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unsigned Offset = 0;
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@ -864,7 +864,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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MinAlign(Alignment, IncrementSize));
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} else {
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Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
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SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
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SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, TLI.getPointerTy()));
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
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@ -1316,7 +1316,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Op, DAG);
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if (Result.getNode())
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if (Result.getNode())
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break;
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case TargetLowering::Legal: {
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LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
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@ -1647,7 +1647,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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if (Tmp2.getValueType() ==
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Op.getValueType().getVectorElementType()) {
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SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
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Tmp1.getValueType(), Tmp2);
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Tmp1.getValueType(), Tmp2);
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unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
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MVT ShufMaskVT =
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@ -1665,7 +1665,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
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}
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SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
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&ShufOps[0], ShufOps.size());
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&ShufOps[0], ShufOps.size());
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Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
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Tmp1, ScVec, ShufMask);
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@ -1709,7 +1709,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
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// Allow targets to custom lower the SHUFFLEs they support.
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switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
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switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())){
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default: assert(0 && "Unknown operation action!");
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case TargetLowering::Legal:
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assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
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@ -1728,7 +1728,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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MVT PtrVT = TLI.getPointerTy();
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SDValue Mask = Node->getOperand(2);
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unsigned NumElems = Mask.getNumOperands();
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SmallVector<SDValue,8> Ops;
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0; i != NumElems; ++i) {
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SDValue Arg = Mask.getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) {
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@ -2475,7 +2475,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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if (Hi.getNode())
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Result = DAG.getNode(ISD::RET, dl, MVT::Other,
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Tmp1, Lo, Tmp3, Hi,Tmp3);
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Tmp1, Lo, Tmp3, Hi, Tmp3);
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else
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Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
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Result = LegalizeOp(Result);
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@ -2510,7 +2510,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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SDValue Lo, Hi;
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SplitVectorOp(Tmp2, Lo, Hi);
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Result = DAG.getNode(ISD::RET, dl, MVT::Other,
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Tmp1, Lo, Tmp3, Hi,Tmp3);
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Tmp1, Lo, Tmp3, Hi, Tmp3);
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Result = LegalizeOp(Result);
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}
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}
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@ -3009,7 +3009,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
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Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
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// Perform the larger operation, then round down.
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Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
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Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
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if (TruncOp != ISD::FP_ROUND)
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Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
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else
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@ -3147,9 +3147,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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TmpEltVT, Tmp2,
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DAG.getIntPtrConstant(i)),
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CC);
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Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
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APInt::getAllOnesValue(EltVT.getSizeInBits()),
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EltVT), DAG.getConstant(0, EltVT));
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Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
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DAG.getConstant(APInt::getAllOnesValue
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(EltVT.getSizeInBits()), EltVT),
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DAG.getConstant(0, EltVT));
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}
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Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
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break;
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@ -4361,7 +4362,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// If this operation is not supported, lower it to 'abort()' call
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Tmp1 = LegalizeOp(Node->getOperand(0));
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TargetLowering::ArgListTy Args;
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std::pair<SDValue,SDValue> CallResult =
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std::pair<SDValue, SDValue> CallResult =
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TLI.LowerCallTo(Tmp1, Type::VoidTy,
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false, false, false, false, CallingConv::C, false,
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DAG.getExternalSymbol("abort", TLI.getPointerTy()),
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@ -5329,7 +5330,7 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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if (!Tmp2.getNode())
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Tmp2 = DAG.getNode(ISD::SETCC, dl,
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TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi,CC);
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LHSHi, RHSHi, CC);
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ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
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ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
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@ -5418,8 +5419,9 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
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MVT DestVT,
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DebugLoc dl) {
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// Create the stack frame object.
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unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
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SrcOp.getValueType().getTypeForMVT());
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unsigned SrcAlign =
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TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
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getTypeForMVT());
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SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
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FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
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@ -5429,8 +5431,8 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
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unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
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unsigned SlotSize = SlotVT.getSizeInBits();
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unsigned DestSize = DestVT.getSizeInBits();
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unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
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DestVT.getTypeForMVT());
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unsigned DestAlign =
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TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
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// Emit a store to the stack slot. Use a truncstore if the input value is
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// later than DestVT.
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@ -5464,8 +5466,8 @@ SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
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int SPFI = StackPtrFI->getIndex();
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SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
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StackPtr,
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PseudoSourceValue::getFixedStack(SPFI), 0);
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StackPtr,
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PseudoSourceValue::getFixedStack(SPFI), 0);
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return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
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PseudoSourceValue::getFixedStack(SPFI), 0);
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}
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@ -5497,7 +5499,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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if (V.getOpcode() != ISD::UNDEF)
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isOnlyLowElement = false;
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if (SplatValue != V)
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SplatValue = SDValue(0,0);
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SplatValue = SDValue(0, 0);
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// If this isn't a constant element or an undef, we can't use a constant
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// pool load.
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@ -5524,7 +5526,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
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CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
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} else if (ConstantSDNode *V =
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dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
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dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
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CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
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} else {
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assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
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@ -5547,7 +5549,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
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std::vector<SDValue> ZeroVec(NumElems, Zero);
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SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
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&ZeroVec[0], ZeroVec.size());
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&ZeroVec[0], ZeroVec.size());
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// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
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if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
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@ -5576,7 +5578,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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else
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Val2 = (++MI)->first;
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// If Val1 is an undef, make sure end ends up as Val2, to ensure that our
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// If Val1 is an undef, make sure it ends up as Val2, to ensure that our
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// vector shuffle has the undef vector on the RHS.
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if (Val1.getOpcode() == ISD::UNDEF)
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std::swap(Val1, Val2);
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@ -5600,7 +5602,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
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SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
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&MaskVec[0], MaskVec.size());
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&MaskVec[0], MaskVec.size());
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// If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
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if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
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@ -5671,7 +5673,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
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/// smaller elements. If we can't find a way that is more efficient than a
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/// libcall on this target, return false. Otherwise, return true with the
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/// low-parts expanded into Lo and Hi.
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bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
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bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
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SDValue &Lo, SDValue &Hi,
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DebugLoc dl) {
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assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
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@ -5698,7 +5700,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
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} else if (Cst > NVTBits) {
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Lo = DAG.getConstant(0, NVT);
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Hi = DAG.getNode(ISD::SHL, dl,
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NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
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NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy));
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} else if (Cst == NVTBits) {
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Lo = DAG.getConstant(0, NVT);
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Hi = InL;
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@ -5716,7 +5718,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
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Hi = DAG.getConstant(0, NVT);
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} else if (Cst > NVTBits) {
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Lo = DAG.getNode(ISD::SRL, dl, NVT,
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InH, DAG.getConstant(Cst-NVTBits,ShTy));
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InH, DAG.getConstant(Cst-NVTBits, ShTy));
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Hi = DAG.getConstant(0, NVT);
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} else if (Cst == NVTBits) {
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Lo = InH;
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@ -5850,7 +5852,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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// Splice the libcall in wherever FindInputOutputChains tells us to.
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const Type *RetTy = Node->getValueType(0).getTypeForMVT();
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std::pair<SDValue,SDValue> CallInfo =
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std::pair<SDValue, SDValue> CallInfo =
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TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
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CallingConv::C, false, Callee, Args, DAG,
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Node->getDebugLoc());
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@ -5914,10 +5916,9 @@ LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
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Tmp1 = PromoteOp(Op);
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if (isSigned) {
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Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
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Tmp1, DAG.getValueType(Op.getValueType()));
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Tmp1, DAG.getValueType(Op.getValueType()));
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} else {
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Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
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Op.getValueType());
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Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType());
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}
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if (Result.getNode())
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Result = DAG.UpdateNodeOperands(Result, Tmp1);
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@ -5984,7 +5985,7 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
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break; // This case is handled below.
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case TargetLowering::Custom: {
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SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
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Source), DAG);
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Source), DAG);
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if (NV.getNode())
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return LegalizeOp(NV);
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break; // The target decided this was legal after all
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@ -6046,7 +6047,7 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
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break; // This case is handled below.
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case TargetLowering::Custom: {
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SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
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Source), DAG);
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Source), DAG);
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if (NV.getNode())
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return LegalizeOp(NV);
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break; // The target decided this was legal after all
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@ -6093,7 +6094,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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// set up Hi and Lo (into buffer) address based on endian
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SDValue Hi = StackSlot;
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SDValue Lo = DAG.getNode(ISD::ADD, dl,
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TLI.getPointerTy(), StackSlot,WordOff);
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TLI.getPointerTy(), StackSlot, WordOff);
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if (TLI.isLittleEndian())
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std::swap(Hi, Lo);
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@ -6108,7 +6109,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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}
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// store the lo of the constructed double - based on integer input
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SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
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Op0Mapped, Lo, NULL, 0);
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Op0Mapped, Lo, NULL, 0);
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// initial hi portion of constructed double
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SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
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// store the hi of the constructed double - biased exponent
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@ -6117,8 +6118,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
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// FP constant to bias correct the final result
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SDValue Bias = DAG.getConstantFP(isSigned ?
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BitsToDouble(0x4330000080000000ULL)
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: BitsToDouble(0x4330000000000000ULL),
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BitsToDouble(0x4330000080000000ULL) :
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BitsToDouble(0x4330000000000000ULL),
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MVT::f64);
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// subtract the bias
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SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
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@ -6454,8 +6455,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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SDValue SrcLo, SrcHi, Src;
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ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
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Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
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SDValue Result = TLI.LowerOperation(
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DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
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SDValue Result =
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TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src,
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Op.getOperand(1)), DAG);
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assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
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Lo = Result.getNode()->getOperand(0);
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Hi = Result.getNode()->getOperand(1);
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@ -6630,7 +6632,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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// Build a factor node to remember that this load is independent of the
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// other one.
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SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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Hi.getValue(1));
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// Remember that we legalized the chain.
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AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
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@ -6643,7 +6645,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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(VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
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// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
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SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
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SVOffset, isVolatile, Alignment);
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SVOffset, isVolatile, Alignment);
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// Remember that we legalized the chain.
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AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
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ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
|
||||
|
|
@ -6829,7 +6831,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
|
|||
SDValue Result = TLI.LowerOperation(Replace, DAG);
|
||||
ExpandOp(Result.getValue(0), Lo, Hi);
|
||||
// Remember that we legalized the chain.
|
||||
AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
|
||||
AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1)));
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -7352,8 +7354,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
|
|||
Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
|
||||
// lo = hi==fabs(hi) ? lo : -lo;
|
||||
Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
|
||||
Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
|
||||
DAG.getCondCode(ISD::SETEQ));
|
||||
Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
|
||||
DAG.getCondCode(ISD::SETEQ));
|
||||
break;
|
||||
}
|
||||
SDValue Mask = (VT == MVT::f64)
|
||||
|
|
@ -7423,9 +7425,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
|
|||
MVT::ppcf128, Node->getOperand(0),
|
||||
DAG.getConstant(0, MVT::i32),
|
||||
DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
|
||||
DAG.getConstantFP(
|
||||
APFloat(APInt(128, 2, TwoE32)),
|
||||
MVT::ppcf128)),
|
||||
DAG.getConstantFP
|
||||
(APFloat(APInt(128, 2, TwoE32)),
|
||||
MVT::ppcf128)),
|
||||
Hi,
|
||||
DAG.getCondCode(ISD::SETLT)),
|
||||
Lo, Hi);
|
||||
|
|
@ -7443,9 +7445,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
|
|||
Node->getOperand(0),
|
||||
DAG.getConstant(0, MVT::i64),
|
||||
DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
|
||||
DAG.getConstantFP(
|
||||
APFloat(APInt(128, 2, TwoE64)),
|
||||
MVT::ppcf128)),
|
||||
DAG.getConstantFP
|
||||
(APFloat(APInt(128, 2, TwoE64)),
|
||||
MVT::ppcf128)),
|
||||
Hi,
|
||||
DAG.getCondCode(ISD::SETLT)),
|
||||
Lo, Hi);
|
||||
|
|
@ -7532,8 +7534,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
|
|||
break;
|
||||
}
|
||||
SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
|
||||
Node->getOperand(1),
|
||||
Node->getOperand(2), dl);
|
||||
Node->getOperand(1),
|
||||
Node->getOperand(2), dl);
|
||||
SplitVectorOp(Tmp, Lo, Hi);
|
||||
break;
|
||||
}
|
||||
|
|
@ -7584,11 +7586,11 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
|
|||
}
|
||||
case ISD::BUILD_VECTOR: {
|
||||
SmallVector<SDValue, 8> LoOps(Node->op_begin(),
|
||||
Node->op_begin()+NewNumElts_Lo);
|
||||
Node->op_begin()+NewNumElts_Lo);
|
||||
Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
|
||||
|
||||
SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
|
||||
Node->op_end());
|
||||
Node->op_end());
|
||||
Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
|
||||
break;
|
||||
}
|
||||
|
|
@ -7605,7 +7607,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
|
|||
&LoOps[0], LoOps.size());
|
||||
|
||||
SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
|
||||
Node->op_end());
|
||||
Node->op_end());
|
||||
Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
|
||||
&HiOps[0], HiOps.size());
|
||||
}
|
||||
|
|
@ -7742,10 +7744,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
|
|||
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
|
||||
SDValue L, H;
|
||||
SplitVectorOp(Node->getOperand(0), L, H);
|
||||
SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
|
||||
SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
|
||||
SDValue STyOpL = DAG.getValueType(L.getValueType());
|
||||
SDValue STyOpH = DAG.getValueType(H.getValueType());
|
||||
SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
|
||||
SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
|
||||
SDValue STyOpL = DAG.getValueType(L.getValueType());
|
||||
SDValue STyOpH = DAG.getValueType(H.getValueType());
|
||||
|
||||
SDValue RndOp = Node->getOperand(3);
|
||||
SDValue SatOp = Node->getOperand(4);
|
||||
|
|
@ -7789,7 +7791,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
|
|||
// Build a factor node to remember that this load is independent of the
|
||||
// other one.
|
||||
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
|
||||
Hi.getValue(1));
|
||||
Hi.getValue(1));
|
||||
|
||||
// Remember that we legalized the chain.
|
||||
AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
|
||||
|
|
@ -7804,14 +7806,14 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
|
|||
// The input is a scalar or single-element vector.
|
||||
// Lower to a store/load so that it can be split.
|
||||
// FIXME: this could be improved probably.
|
||||
unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
|
||||
Op.getValueType().getTypeForMVT());
|
||||
unsigned LdAlign = TLI.getTargetData()->
|
||||
getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
|
||||
SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
|
||||
int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
|
||||
|
||||
SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
|
||||
InOp, Ptr,
|
||||
PseudoSourceValue::getFixedStack(FI), 0);
|
||||
InOp, Ptr,
|
||||
PseudoSourceValue::getFixedStack(FI), 0);
|
||||
InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
|
||||
PseudoSourceValue::getFixedStack(FI), 0);
|
||||
}
|
||||
|
|
@ -8441,7 +8443,7 @@ SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
|
|||
EVTWidth = EVT.getSizeInBits();
|
||||
|
||||
SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
|
||||
isVolatile, Alignment);
|
||||
isVolatile, Alignment);
|
||||
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
|
||||
LdChain.push_back(LdOp.getValue(1));
|
||||
|
||||
|
|
@ -8473,8 +8475,8 @@ SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
|
|||
}
|
||||
|
||||
SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
|
||||
SVOffset+Offset, isVolatile,
|
||||
MinAlign(Alignment, Offset));
|
||||
SVOffset+Offset, isVolatile,
|
||||
MinAlign(Alignment, Offset));
|
||||
LdChain.push_back(LdOp.getValue(1));
|
||||
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
|
||||
DAG.getIntPtrConstant(Idx++));
|
||||
|
|
@ -8553,7 +8555,7 @@ void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
|
|||
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
|
||||
DAG.getIntPtrConstant(0));
|
||||
SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
|
||||
isVolatile, Alignment);
|
||||
isVolatile, Alignment);
|
||||
StChain.push_back(StOp);
|
||||
|
||||
// Check if we are done
|
||||
|
|
@ -8593,8 +8595,8 @@ void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
|
|||
|
||||
|
||||
SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
|
||||
SDValue Chain,
|
||||
SDValue BasePtr) {
|
||||
SDValue Chain,
|
||||
SDValue BasePtr) {
|
||||
// TODO: It might be cleaner if we can use SplitVector and have more legal
|
||||
// vector types that can be stored into memory (e.g., v4xi8 can
|
||||
// be stored as a word). This will not work when a vector register
|
||||
|
|
|
|||
Loading…
Reference in New Issue