forked from OSchip/llvm-project
[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support
Move 'lowest' demanded elt -> bitcast fold out of ZERO_EXTEND_VECTOR_INREG into ANY_EXTEND_VECTOR_INREG case. llvm-svn: 363856
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@ -1381,19 +1381,11 @@ bool TargetLowering::SimplifyDemandedBits(
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bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
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// If none of the top bits are demanded, convert this into an any_extend.
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if (DemandedBits.getActiveBits() <= InBits) {
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// If we only need the non-extended bits of the bottom element
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// then we can just bitcast to the result.
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if (IsVecInReg && DemandedElts == 1 &&
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VT.getSizeInBits() == SrcVT.getSizeInBits() &&
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TLO.DAG.getDataLayout().isLittleEndian())
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return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
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if (DemandedBits.getActiveBits() <= InBits)
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return TLO.CombineTo(
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Op, TLO.DAG.getNode(IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG
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: ISD::ANY_EXTEND,
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dl, VT, Src));
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}
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APInt InDemandedBits = DemandedBits.trunc(InBits);
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APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
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@ -1444,12 +1436,21 @@ bool TargetLowering::SimplifyDemandedBits(
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dl, VT, Src));
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break;
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}
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case ISD::ANY_EXTEND: {
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// TODO: Add ISD::ANY_EXTEND_VECTOR_INREG support.
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case ISD::ANY_EXTEND:
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case ISD::ANY_EXTEND_VECTOR_INREG: {
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SDValue Src = Op.getOperand(0);
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EVT SrcVT = Src.getValueType();
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unsigned InBits = SrcVT.getScalarSizeInBits();
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unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
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bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
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// If we only need the bottom element then we can just bitcast.
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// TODO: Handle ANY_EXTEND?
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if (IsVecInReg && DemandedElts == 1 &&
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VT.getSizeInBits() == SrcVT.getSizeInBits() &&
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TLO.DAG.getDataLayout().isLittleEndian())
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return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
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APInt InDemandedBits = DemandedBits.trunc(InBits);
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APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);
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if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
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