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Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too." 

This reverts commit r191130.

llvm-svn: 191138
This commit is contained in:
Juergen Ributzka 2013-09-21 15:09:46 +00:00
parent cf627f0f7b
commit f043a65327
4 changed files with 9 additions and 83 deletions
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21
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -4327,27 +4327,6 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
}
}
// Treat SETCC as a mask and promote the result type based on the targets
// expected SETCC result type. This will ensure that SETCC and VSELECT are
// both split by the type legalizer. This is done to prevent the type
// legalizer from unrolling SETCC into scalar comparions.
EVT SelectVT = N->getValueType(0);
if (N0.getOpcode() == ISD::SETCC &&
N0.getValueType() != getSetCCResultType(SelectVT)) {
SDLoc MaskDL(N0);
EVT MaskVT = getSetCCResultType(SelectVT);
SDValue Mask = DAG.getNode(ISD::SETCC, MaskDL, MaskVT, N0->getOperand(0),
N0->getOperand(1), N0->getOperand(2));
AddToWorkList(Mask.getNode());
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
return DAG.getNode(ISD::VSELECT, DL, SelectVT, Mask, LHS, RHS);
}
return SDValue();
}

22
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -489,20 +489,14 @@ void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
SDValue Cond = N->getOperand(0);
CL = CH = Cond;
if (Cond.getValueType().isVector()) {
if (Cond.getOpcode() == ISD::SETCC) {
assert(Cond.getValueType() == getSetCCResultType(N->getValueType(0)) &&
"Condition has not been prepared for split!");
GetSplitVector(Cond, CL, CH);
} else {
assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
"Condition legalized before result?");
unsigned NumElements = Cond.getValueType().getVectorNumElements();
EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
DAG.getConstant(0, TLI.getVectorIdxTy()));
CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
}
assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
"Condition legalized before result?");
unsigned NumElements = Cond.getValueType().getVectorNumElements();
EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
DAG.getConstant(0, TLI.getVectorIdxTy()));
CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
}
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);

11
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -1535,16 +1535,7 @@ void X86TargetLowering::resetOperationActions() {
}
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
if (!VT.isVector())
return MVT::i8;
const TargetMachine &TM = getTargetMachine();
if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
switch(VT.getVectorNumElements()) {
case 8: return MVT::v8i1;
case 16: return MVT::v16i1;
}
if (!VT.isVector()) return MVT::i8;
return VT.changeVectorElementTypeToInteger();
}

38
llvm/test/CodeGen/X86/vec_split.ll
View File

@ -1,38 +0,0 @@
; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4
; RUN: llc -march=x86-64 -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1
; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) {
; SSE4-LABEL: split16:
; SSE4: pminuw
; SSE4: pminuw
; AVX1-LABEL: split16:
; AVX1: vpminuw
; AVX1: vpminuw
; AVX2-LABEL: split16:
; AVX2: vpminuw
; AVX2: ret
%1 = icmp ult <16 x i16> %a, %b
%2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
ret <16 x i16> %2
}
define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) {
; SSE4-LABEL: split32:
; SSE4: pminuw
; SSE4: pminuw
; SSE4: pminuw
; SSE4: pminuw
; AVX1-LABEL: split32:
; AVX1: vpminuw
; AVX1: vpminuw
; AVX1: vpminuw
; AVX1: vpminuw
; AVX2-LABEL: split32:
; AVX2: vpminuw
; AVX2: vpminuw
; AVX2: ret
%1 = icmp ult <32 x i16> %a, %b
%2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b
ret <32 x i16> %2
}