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Print another class of instructions correctly, giving us: xorl EDX, EDX 

for example.

llvm-svn: 4793
This commit is contained in:
Chris Lattner 2002-11-21 00:30:01 +00:00
parent 95e6287734
commit f03132f014
1 changed files with 37 additions and 15 deletions
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52
llvm/lib/Target/X86/Printer.cpp
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@ -97,6 +97,12 @@ static std::ostream &toHex(std::ostream &O, unsigned char V) {
} }
static bool isReg(const MachineOperand &MO) {
return MO.getType()==MachineOperand::MO_VirtualRegister ||
MO.getType()==MachineOperand::MO_MachineRegister;
}
// print - Print out an x86 instruction in intel syntax // print - Print out an x86 instruction in intel syntax
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const { const TargetMachine &TM) const {
@ -137,20 +143,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
// //
// 2 Operands: this is for things like mov that do not read a second input // 2 Operands: this is for things like mov that do not read a second input
// //
assert(((MI->getNumOperands() == 3 && assert(isReg(MI->getOperand(0)) &&
(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister|| (MI->getNumOperands() == 2 ||
MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister) (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
&& isReg(MI->getOperand(MI->getNumOperands()-1))
(MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister||
MI->getOperand(1).getType()==MachineOperand::MO_MachineRegister))
||
(MI->getNumOperands() == 2 &&
(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister||
MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister)
&& (MI->getOperand(MI->getNumOperands()-1).getType() ==
MachineOperand::MO_VirtualRegister||
MI->getOperand(MI->getNumOperands()-1).getType() ==
MachineOperand::MO_MachineRegister)))
&& "Bad format for MRMDestReg!"); && "Bad format for MRMDestReg!");
if (MI->getNumOperands() == 3 && if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
@ -163,8 +159,34 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
O << "\n"; O << "\n";
return; return;
case X86II::MRMDestMem:
case X86II::MRMSrcReg: case X86II::MRMSrcReg:
// There is a two forms that are acceptable for MRMSrcReg instructions,
// those with 3 and 2 operands:
//
// 3 Operands: in this form, the last register (the second input) is the
// ModR/M input. The first two operands should be the same, post register
// allocation. This is for things like: add r32, r/m32
//
// 2 Operands: this is for things like mov that do not read a second input
//
assert(isReg(MI->getOperand(0)) &&
isReg(MI->getOperand(1)) &&
(MI->getNumOperands() == 2 ||
(MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
&& "Bad format for MRMDestReg!");
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";
O << "\t";
O << getName(MI->getOpCode()) << " ";
printOp(O, MI->getOperand(0), RI);
O << ", ";
printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
O << "\n";
return;
case X86II::MRMDestMem:
case X86II::MRMSrcMem: case X86II::MRMSrcMem:
default: default:
O << "\t-"; MI->print(O, TM); break; O << "\t-"; MI->print(O, TM); break;