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[NFCI] Fixed missing colon in CHECK directives

This commit is contained in:
Dávid Bolvanský 2022-04-03 11:51:33 +02:00
parent fbfd78f7aa
commit f02a0a69af
11 changed files with 127 additions and 68 deletions
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16
llvm/test/Analysis/MemorySSA/print-dot-cfg-mssa.ll
View File

@ -85,11 +85,11 @@ declare void @g(...)
; CHECK-NEXT: label="MSSA";
; CHECK: {{Node0x.* [shape=record,label="{entry:.*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{bb1:.*1 = MemoryDef(liveOnEntry).*2 = MemoryDef(1).*3 = MemoryDef(2).*4 = MemoryDef(3).*MemoryUse(3).*MemoryUse(liveOnEntry).*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{if.then:.*5 = MemoryDef(4).*}"]}}
; CHECK {{[shape=record,label="{bb2:.*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{if.else:.*6 = MemoryDef(4).*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{if.end:.*10 = MemoryPhi({bb2,5},{if.else,6})/*MemoryUse(2).*MemoryUse(10).*MemoryUse(1).*7 = MemoryDef(10).*MemoryUse(10).*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{if.then2:.*MemoryUse(10).*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{bb3:.*8 = MemoryDef(7).*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{if.end3:.*9 = MemoryPhi({if.end,7},{bb3,8}).*}"]}}
; CHECK {{[shape=record,style=filled, fillcolor=lightpink,label="{bb4:.*MemoryUse(2).*MemoryUse(7).*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{if.then:.*5 = MemoryDef(4).*}"]}}
; CHECK: {{[shape=record,label="{bb2:.*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{if.else:.*6 = MemoryDef(4).*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{if.end:.*10 = MemoryPhi({bb2,5},{if.else,6})/*MemoryUse(2).*MemoryUse(10).*MemoryUse(1).*7 = MemoryDef(10).*MemoryUse(10).*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{if.then2:.*MemoryUse(10).*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{bb3:.*8 = MemoryDef(7).*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{if.end3:.*9 = MemoryPhi({if.end,7},{bb3,8}).*}"]}}
; CHECK: {{[shape=record,style=filled, fillcolor=lightpink,label="{bb4:.*MemoryUse(2).*MemoryUse(7).*}"]}}

4
llvm/test/Analysis/ScalarEvolution/trivial-phis.ll
View File

@ -1,8 +1,8 @@
; RUN: opt -passes='print<scalar-evolution>' -disable-output %s 2>&1 | FileCheck %s
; CHECK-LABEL @test1
; CHECK %add.lcssa.wide = phi i64 [ %indvars.iv.next, %do.body ]
; CHECK-NEXT --> %add.lcssa.wide U: [1,2147483648) S: [1,2147483648)
; CHECK: %add.lcssa.wide = phi i64 [ %indvars.iv.next, %do.body ]
; CHECK-NEXT: --> %add.lcssa.wide U: [1,2147483648) S: [1,2147483648)
define i64 @test1(i32 signext %n, float* %A) {
entry:

6
llvm/test/CodeGen/NVPTX/lower-byval-args.ll
View File

@ -17,7 +17,7 @@
; CHECK32: cvta.to.global.u32 [[result_addr_g:%r[0-9]+]], [[result_addr]]
;
; CHECK: ld.param.u32 [[value:%r[0-9]+]], [%[[param_addr1]]+12];
; CHECK st.global.u32 [[[result_addr_g]]], [[value]];
; CHECK: st.global.u32 [[[result_addr_g]]], [[value]];
; Function Attrs: nofree norecurse nounwind willreturn mustprogress
define dso_local void @static_offset(i32* nocapture %arg, %struct.ham* nocapture readonly byval(%struct.ham) align 4 %arg1, i32 %arg2) local_unnamed_addr #0 {
bb:
@ -50,7 +50,7 @@ bb6: ; preds = %bb3, %bb
; CHECK32: add.s32 %[[param_w_offset:r[0-9]+]], %[[param_addr1]],
;
; CHECK: ld.param.u32 [[value:%r[0-9]+]], [%[[param_w_offset]]];
; CHECK st.global.u32 [[[result_addr_g]]], [[value]];
; CHECK: st.global.u32 [[[result_addr_g]]], [[value]];
; Function Attrs: nofree norecurse nounwind willreturn mustprogress
define dso_local void @dynamic_offset(i32* nocapture %arg, %struct.ham* nocapture readonly byval(%struct.ham) align 4 %arg1, i32 %arg2) local_unnamed_addr #0 {
@ -136,7 +136,7 @@ bb:
; CHECK32: cvta.to.global.u32 [[result_addr_g:%r[0-9]+]], [[result_addr]]
; CHECK32: add.s32 %[[copy_w_offset:r[0-9]+]], %[[copy_addr]],
; CHECK: ld.local.u32 [[value:%r[0-9]+]], [%[[copy_w_offset]]];
; CHECK st.global.u32 [[[result_addr_g]]], [[value]];
; CHECK: st.global.u32 [[[result_addr_g]]], [[value]];
; Function Attrs: convergent norecurse nounwind mustprogress
define dso_local void @pointer_escapes(i32* nocapture %arg, %struct.ham* byval(%struct.ham) align 4 %arg1, i32 %arg2) local_unnamed_addr #1 {

59
llvm/test/CodeGen/Thumb2/bti-outliner-1.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s
; Check that each outlining candidate and the outlined function are in agreement
@ -30,6 +31,19 @@
@f = hidden global i32 0, align 4
define hidden i32 @x(i32 %p) local_unnamed_addr #0 {
; CHECK-LABEL: x:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r0, .LCPI0_0
; CHECK-NEXT: .save {lr}
; CHECK-NEXT: str lr, [sp, #-8]!
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: ldr lr, [sp], #8
; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long .L_MergedGlobals
entry:
%0 = load volatile i32, i32* @a, align 4
%1 = load volatile i32, i32* @b, align 4
@ -45,11 +59,21 @@ entry:
%add3 = add nsw i32 %add2, 1
ret i32 %add3
}
; CHECK-LABEL: x:
; CHECK-NOT: bti
; CHECK: bl OUTLINED_FUNCTION_0
define hidden i32 @y(i32 %p) local_unnamed_addr #1 {
; CHECK-LABEL: y:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r0, .LCPI1_0
; CHECK-NEXT: .save {lr}
; CHECK-NEXT: str lr, [sp, #-8]!
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: ldr lr, [sp], #8
; CHECK-NEXT: adds r0, #2
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI1_0:
; CHECK-NEXT: .long .L_MergedGlobals
entry:
%0 = load volatile i32, i32* @a, align 4
%1 = load volatile i32, i32* @b, align 4
@ -65,11 +89,28 @@ entry:
%add3 = add nsw i32 %add2, 2
ret i32 %add3
}
; CHECK-LABEL: y:
; CHECK-NOT: bti
; CHECK: bl OUTLINED_FUNCTION_0
define hidden i32 @z(i32 %p) local_unnamed_addr #2 {
; CHECK-LABEL: z:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: bti
; CHECK-NEXT: ldr r0, .LCPI2_0
; CHECK-NEXT: ldr r1, [r0]
; CHECK-NEXT: ldr r2, [r0, #4]
; CHECK-NEXT: add r1, r2
; CHECK-NEXT: ldr r2, [r0, #8]
; CHECK-NEXT: ldr r3, [r0, #12]
; CHECK-NEXT: add r2, r3
; CHECK-NEXT: sdiv r1, r1, r2
; CHECK-NEXT: ldr r2, [r0, #16]
; CHECK-NEXT: ldr r0, [r0, #20]
; CHECK-NEXT: mla r0, r2, r1, r0
; CHECK-NEXT: adds r0, #3
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI2_0:
; CHECK-NEXT: .long .L_MergedGlobals
entry:
%0 = load volatile i32, i32* @a, align 4
%1 = load volatile i32, i32* @b, align 4
@ -85,12 +126,6 @@ entry:
%add3 = add nsw i32 %add2, 3
ret i32 %add3
}
; CHECK-LABEL: z:
; CHECK bti
; CHECK-NOT: bl OUTLINED_FUNCTION
; CHECK-LABEL: OUTLINED_FUNCTION_0:
; CHECK-NOT: bti
attributes #0 = { minsize nofree norecurse nounwind optsize }
attributes #1 = { minsize nofree norecurse nounwind optsize "branch-target-enforcement"="false" }

4
llvm/test/CodeGen/X86/text-section-prefix.ll
View File

@ -4,7 +4,7 @@
; RUN: llc -mtriple x86_64-windows-gnu -function-sections %s -o - | FileCheck %s --check-prefix=COFF-GNU
define void @foo1(i1 zeroext %0) nounwind !section_prefix !0 {
;; CHECK hot section name
;; Check hot section name
; ELF: .section .text.hot.foo1,"ax",@progbits
; ELF-NOUNIQ: .section .text.hot.,"ax",@progbits,unique,1
; COFF-MSVC: .section .text$hot,"xr",one_only,foo1
@ -13,7 +13,7 @@ define void @foo1(i1 zeroext %0) nounwind !section_prefix !0 {
}
define void @foo2(i1 zeroext %0) nounwind !section_prefix !1 {
;; CHECK unlikely section name
;; Check unlikely section name
; ELF: .section .text.unlikely.foo2,"ax",@progbits
; ELF-NOUNIQ: .section .text.unlikely.,"ax",@progbits,unique,2
; COFF-MSVC: .section .text$unlikely,"xr",one_only,foo2

12
llvm/test/DebugInfo/X86/dwarfdump-over.ll
View File

@ -12,13 +12,13 @@
; CHECK: DW_AT_upper_bound (DW_OP_push_object_address, DW_OP_over, DW_OP_constu 0x30, DW_OP_mul, DW_OP_plus_uconst 0x78, DW_OP_plus, DW_OP_deref)
; CHECK: DW_AT_byte_stride (DW_OP_push_object_address, DW_OP_over, DW_OP_constu 0x30, DW_OP_mul, DW_OP_plus_uconst 0x70, DW_OP_plus, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
; CHECK: DW_TAG_subrange_type
; CHECK DW_AT_lower_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0x80, DW_OP_deref)
; CHECK DW_AT_upper_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0xa8, DW_OP_deref)
; CHECK DW_AT_byte_stride (DW_OP_push_object_address, DW_OP_plus_uconst 0xa0, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
; CHECK: DW_AT_lower_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0x80, DW_OP_deref)
; CHECK: DW_AT_upper_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0xa8, DW_OP_deref)
; CHECK: DW_AT_byte_stride (DW_OP_push_object_address, DW_OP_plus_uconst 0xa0, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
; CHECK: DW_TAG_subrange_type
; CHECK DW_AT_lower_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0xb0, DW_OP_deref)
; CHECK DW_AT_upper_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0xd8, DW_OP_deref)
; CHECK DW_AT_byte_stride (DW_OP_push_object_address, DW_OP_plus_uconst 0xd0, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
; CHECK: DW_AT_lower_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0xb0, DW_OP_deref)
; CHECK: DW_AT_upper_bound (DW_OP_push_object_address, DW_OP_plus_uconst 0xd8, DW_OP_deref)
; CHECK: DW_AT_byte_stride (DW_OP_push_object_address, DW_OP_plus_uconst 0xd0, DW_OP_deref, DW_OP_lit4, DW_OP_mul)
; Test case is hand written with the help of below Fortran source program.
; Generated IR is meaning less and goal of it is just to check the

2
llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
View File

@ -112,7 +112,7 @@ define float @test_shrink_libcall_trunc(float %C) {
}
; This is replaced with the intrinsic, which does the right thing on
; CHECK platforms.
; tested platforms.
define float @test_shrink_libcall_fabs(float %C) {
; CHECK-LABEL: @test_shrink_libcall_fabs(
; CHECK-NEXT: [[F:%.*]] = call float @llvm.fabs.f32(float [[C:%.*]])

2
llvm/test/Transforms/LoopFusion/cannot_fuse.ll
View File

@ -3,7 +3,7 @@
@B = common global [1024 x i32] zeroinitializer, align 16
; CHECK that the two candidates for fusion are placed into separate candidate
; Check that the two candidates for fusion are placed into separate candidate
; sets because they are not control flow equivalent.
; CHECK: Performing Loop Fusion on function non_cfe

48
llvm/test/Transforms/LoopStrengthReduce/scaling-factor-incompat-type.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; Check that it doesn't crash by generating formula with zero in base register
; when one of the IV factors does't fit (2^32 in this test) the formula type
; see pr42770
@ -6,32 +7,47 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
; CHECK-LABEL: @foo(
define void @foo() {
; CHECK-LABEL: @foo(
; CHECK-NEXT: bb:
; CHECK-NEXT: br label [[BB4:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[T3:%.*]] = ashr i64 [[LSR_IV_NEXT:%.*]], 32
; CHECK-NEXT: ret void
; CHECK: bb4:
; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i16 [ [[LSR_IV_NEXT2:%.*]], [[BB13:%.*]] ], [ 6, [[BB:%.*]] ]
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT]], [[BB13]] ], [ 8589934593, [[BB]] ]
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 25769803776
; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i16 [[LSR_IV1]], 6
; CHECK-NEXT: [[T10:%.*]] = icmp eq i16 1, 0
; CHECK-NEXT: br i1 [[T10]], label [[BB11:%.*]], label [[BB13]]
; CHECK: bb11:
; CHECK-NEXT: [[T12:%.*]] = udiv i16 1, [[LSR_IV1]]
; CHECK-NEXT: unreachable
; CHECK: bb13:
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB4]]
;
bb:
br label %bb4
; CHECK: bb1:
; CHECK: %tmp3 = ashr i64 %lsr.iv.next, 32
bb1: ; preds = %bb13
%tmp = shl i64 %tmp14, 32
%tmp2 = add i64 %tmp, 1
%tmp3 = ashr i64 %tmp2, 32
%t = shl i64 %t14, 32
%t2 = add i64 %t, 1
%t3 = ashr i64 %t2, 32
ret void
; CHECK bb4:
bb4: ; preds = %bb13, %bb
%tmp5 = phi i64 [ 2, %bb ], [ %tmp14, %bb13 ]
%tmp6 = add i64 %tmp5, 4
%tmp7 = trunc i64 %tmp6 to i16
%tmp8 = urem i16 %tmp7, 3
%tmp9 = mul i16 %tmp8, 2
%tmp10 = icmp eq i16 %tmp9, 1
br i1 %tmp10, label %bb11, label %bb13
%t5 = phi i64 [ 2, %bb ], [ %t14, %bb13 ]
%t6 = add i64 %t5, 4
%t7 = trunc i64 %t6 to i16
%t8 = urem i16 %t7, 3
%t9 = mul i16 %t8, 2
%t10 = icmp eq i16 %t9, 1
br i1 %t10, label %bb11, label %bb13
bb11: ; preds = %bb4
%tmp12 = udiv i16 1, %tmp7
%t12 = udiv i16 1, %t7
unreachable
bb13: ; preds = %bb4
%tmp14 = add nuw nsw i64 %tmp5, 6
%t14 = add nuw nsw i64 %t5, 6
br i1 undef, label %bb1, label %bb4
}

16
llvm/test/Transforms/SCCP/clang-arc-rv.ll
View File

@ -1,21 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=ipsccp -S | FileCheck %s
; Return value can't be zapped if there is a call that has operand bundle
; "clang.arc.attachedcall".
@g0 = global i8 zeroinitializer, align 1
; CHECK-LABEL: @foo(
; CHECK: ret i8* @g0
define internal i8* @foo() {
; CHECK-LABEL: @foo(
; CHECK-NEXT: ret i8* @g0
;
ret i8* @g0
}
; CHECK-LABEL: @test(
; CHECK: %[[R:.*]] = call i8* @foo()
; CHECK call void (...) @llvm.objc.clang.arc.noop.use(i8* %[[R]])
define void @test() {
; CHECK-LABEL: @test(
; CHECK-NEXT: [[R:%.*]] = call i8* @foo() [ "clang.arc.attachedcall"(i8* (i8*)* @llvm.objc.unsafeClaimAutoreleasedReturnValue) ]
; CHECK-NEXT: call void (...) @llvm.objc.clang.arc.noop.use(i8* [[R]])
; CHECK-NEXT: ret void
;
%r = call i8* @foo() [ "clang.arc.attachedcall"(i8* (i8*)* @llvm.objc.unsafeClaimAutoreleasedReturnValue) ]
call void (...) @llvm.objc.clang.arc.noop.use(i8* %r)
ret void

26
llvm/test/Transforms/SampleProfile/gcc-simple.ll
View File

@ -33,9 +33,10 @@ entry:
store i64 %i, i64* %i.addr, align 8
call void @llvm.dbg.declare(metadata i64* %i.addr, metadata !16, metadata !17), !dbg !18
%call = call i32 @rand() #3, !dbg !19
; CHECK: !prof ![[PROF1:[0-9]+]]
%cmp = icmp slt i32 %call, 500, !dbg !21
br i1 %cmp, label %if.then, label %if.else, !dbg !22
; CHECK: !prof ![[PROF1:[0-9]+]]
; CHECK: !prof ![[PROF2:[0-9]+]]
if.then: ; preds = %entry
store i64 2, i64* %retval, align 8, !dbg !23
@ -43,9 +44,10 @@ if.then: ; preds = %entry
if.else: ; preds = %entry
%call1 = call i32 @rand() #3, !dbg !25
; CHECK: !prof ![[PROF3:[0-9]+]]
%cmp2 = icmp sgt i32 %call1, 5000, !dbg !28
br i1 %cmp2, label %if.then.3, label %if.else.4, !dbg !29
; CHECK: !prof ![[PROF2:[0-9]+]]
; CHECK: !prof ![[PROF4:[0-9]+]]
if.then.3: ; preds = %if.else
store i64 10, i64* %retval, align 8, !dbg !30
@ -85,7 +87,7 @@ for.cond: ; preds = %for.inc.4, %entry
%0 = load i32, i32* %k, align 4, !dbg !41
%cmp = icmp slt i32 %0, 3000, !dbg !45
br i1 %cmp, label %for.body, label %for.end.6, !dbg !46
; CHECK: !prof ![[PROF3:[0-9]+]]
; CHECK: !prof ![[PROF6:[0-9]+]]
for.body: ; preds = %for.cond
call void @llvm.dbg.declare(metadata i32* %i, metadata !47, metadata !17), !dbg !49
@ -96,12 +98,13 @@ for.cond.1: ; preds = %for.inc, %for.body
%1 = load i32, i32* %i, align 4, !dbg !51
%cmp2 = icmp slt i32 %1, 200000, !dbg !55
br i1 %cmp2, label %for.body.3, label %for.end, !dbg !56
; CHECK: !prof ![[PROF4:[0-9]+]]
; CHECK: !prof ![[PROF7:[0-9]+]]
for.body.3: ; preds = %for.cond.1
%2 = load i32, i32* %i, align 4, !dbg !57
%conv = sext i32 %2 to i64, !dbg !57
%call = call i64 @_Z3fool(i64 %conv), !dbg !59
; CHECK: !prof ![[PROF8:[0-9]+]]
%3 = load i64, i64* %sum, align 8, !dbg !60
%add = add nsw i64 %3, %call, !dbg !60
store i64 %add, i64* %sum, align 8, !dbg !60
@ -129,12 +132,15 @@ for.end.6: ; preds = %for.cond
ret i32 %cond, !dbg !71
}
; CHECK ![[EC1]] = !{!"function_entry_count", i64 24108}
; CHECK ![[PROF1]] = !{!"branch_weights", i32 1, i32 30124}
; CHECK ![[PROF2]] = !{!"branch_weights", i32 30177, i32 29579}
; CHECK ![[EC2]] = !{!"function_entry_count", i64 0}
; CHECK ![[PROF3]] = !{!"branch_weights", i32 1, i32 1}
; CHECK ![[PROF4]] = !{!"branch_weights", i32 1, i32 20238}
; CHECK: ![[EC1]] = !{!"function_entry_count", i64 24109}
; CHECK: ![[PROF1]] = !{!"branch_weights", i32 24109}
; CHECK: ![[PROF2]] = !{!"branch_weights", i32 30125, i32 30125}
; CHECK: ![[PROF3]] = !{!"branch_weights", i32 30124}
; CHECK: ![[PROF4]] = !{!"branch_weights", i32 30125, i32 29580}
; CHECK: ![[EC2]] = !{!"function_entry_count", i64 1}
; CHECK: ![[PROF6]] = !{!"branch_weights", i32 1, i32 2}
; CHECK: ![[PROF7]] = !{!"branch_weights", i32 18943, i32 1}
; CHECK: ![[PROF8]] = !{!"branch_weights", i32 18942}
attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" "use-sample-profile" }
attributes #1 = { nounwind readnone }