forked from OSchip/llvm-project
[X86] Use for loops over types to reduce code for setting up operation actions. NFC
llvm-svn: 265871
This commit is contained in:
Craig Topper
parent
e801ed9e15
commit
f027107094
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@ -1060,29 +1060,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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}
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if (Subtarget.hasXOP()) {
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setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
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setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
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setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
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setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
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setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
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setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
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setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
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setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
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MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
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setOperationAction(ISD::ROTL, VT, Custom);
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// XOP can efficiently perform BITREVERSE with VPPERM.
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setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::i16, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::i64, Custom);
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for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
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setOperationAction(ISD::BITREVERSE, VT, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v8i16, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v4i32, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v2i64, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v16i16, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v8i32, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::v4i64, Custom);
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
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MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
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setOperationAction(ISD::BITREVERSE, VT, Custom);
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}
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if (!Subtarget.useSoftFloat() && Subtarget.hasFp256()) {
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@ -1097,31 +1085,20 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
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setOperationAction(ISD::FADD, MVT::v8f32, Legal);
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setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
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setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
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setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
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setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
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setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
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setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
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setOperationAction(ISD::FABS, MVT::v8f32, Custom);
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setOperationAction(ISD::FADD, MVT::v4f64, Legal);
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setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
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setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
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setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
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setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
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setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
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setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
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setOperationAction(ISD::FABS, MVT::v4f64, Custom);
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for (auto VT : { MVT::v8f32, MVT::v4f64 }) {
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setOperationAction(ISD::FADD, VT, Legal);
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setOperationAction(ISD::FSUB, VT, Legal);
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setOperationAction(ISD::FMUL, VT, Legal);
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setOperationAction(ISD::FDIV, VT, Legal);
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setOperationAction(ISD::FSQRT, VT, Legal);
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setOperationAction(ISD::FFLOOR, VT, Legal);
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setOperationAction(ISD::FCEIL, VT, Legal);
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setOperationAction(ISD::FTRUNC, VT, Legal);
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setOperationAction(ISD::FRINT, VT, Legal);
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setOperationAction(ISD::FNEARBYINT, VT, Legal);
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setOperationAction(ISD::FNEG, VT, Custom);
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setOperationAction(ISD::FABS, VT, Custom);
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}
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// (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
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// even though v8i16 is a legal type.
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@ -1139,14 +1116,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (MVT VT : MVT::fp_vector_valuetypes())
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
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setOperationAction(ISD::SRL, MVT::v16i16, Custom);
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setOperationAction(ISD::SRL, MVT::v32i8, Custom);
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setOperationAction(ISD::SHL, MVT::v16i16, Custom);
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setOperationAction(ISD::SHL, MVT::v32i8, Custom);
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setOperationAction(ISD::SRA, MVT::v16i16, Custom);
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setOperationAction(ISD::SRA, MVT::v32i8, Custom);
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for (auto VT : { MVT::v32i8, MVT::v16i16 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
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setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
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@ -1170,39 +1144,23 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
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setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
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setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
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setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
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setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
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setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
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setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
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setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
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setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTTZ, VT, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
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}
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if (Subtarget.hasAnyFMA()) {
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setOperationAction(ISD::FMA, MVT::v8f32, Legal);
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setOperationAction(ISD::FMA, MVT::v4f64, Legal);
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setOperationAction(ISD::FMA, MVT::v4f32, Legal);
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setOperationAction(ISD::FMA, MVT::v2f64, Legal);
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setOperationAction(ISD::FMA, MVT::f32, Legal);
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setOperationAction(ISD::FMA, MVT::f64, Legal);
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for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
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MVT::v2f64, MVT::v4f64 })
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setOperationAction(ISD::FMA, VT, Legal);
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}
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if (Subtarget.hasInt256()) {
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setOperationAction(ISD::ADD, MVT::v4i64, Legal);
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setOperationAction(ISD::ADD, MVT::v8i32, Legal);
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setOperationAction(ISD::ADD, MVT::v16i16, Legal);
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setOperationAction(ISD::ADD, MVT::v32i8, Legal);
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setOperationAction(ISD::SUB, MVT::v4i64, Legal);
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setOperationAction(ISD::SUB, MVT::v8i32, Legal);
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setOperationAction(ISD::SUB, MVT::v16i16, Legal);
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setOperationAction(ISD::SUB, MVT::v32i8, Legal);
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::ADD, VT, Legal);
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setOperationAction(ISD::SUB, VT, Legal);
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}
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setOperationAction(ISD::MUL, MVT::v4i64, Custom);
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setOperationAction(ISD::MUL, MVT::v8i32, Legal);
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@ -1217,18 +1175,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
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setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
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setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
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setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
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setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
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setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
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setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
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setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
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setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
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setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
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setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
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setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
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setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
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setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
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setOperationAction(ISD::SMAX, VT, Legal);
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setOperationAction(ISD::UMAX, VT, Legal);
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setOperationAction(ISD::SMIN, VT, Legal);
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setOperationAction(ISD::UMIN, VT, Legal);
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}
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom);
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@ -1253,15 +1205,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
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} else {
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setOperationAction(ISD::ADD, MVT::v4i64, Custom);
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setOperationAction(ISD::ADD, MVT::v8i32, Custom);
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setOperationAction(ISD::ADD, MVT::v16i16, Custom);
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setOperationAction(ISD::ADD, MVT::v32i8, Custom);
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setOperationAction(ISD::SUB, MVT::v4i64, Custom);
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setOperationAction(ISD::SUB, MVT::v8i32, Custom);
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setOperationAction(ISD::SUB, MVT::v16i16, Custom);
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setOperationAction(ISD::SUB, MVT::v32i8, Custom);
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::ADD, VT, Custom);
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setOperationAction(ISD::SUB, VT, Custom);
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}
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setOperationAction(ISD::MUL, MVT::v4i64, Custom);
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setOperationAction(ISD::MUL, MVT::v8i32, Custom);
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@ -1276,30 +1223,21 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
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setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
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setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
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setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
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setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
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setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
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setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
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setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
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setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
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setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
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setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
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setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
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setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
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setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
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for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
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setOperationAction(ISD::SMAX, VT, Custom);
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setOperationAction(ISD::UMAX, VT, Custom);
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setOperationAction(ISD::SMIN, VT, Custom);
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setOperationAction(ISD::UMIN, VT, Custom);
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}
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}
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// In the customized shift lowering, the legal cases in AVX2 will be
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// recognized.
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setOperationAction(ISD::SRL, MVT::v4i64, Custom);
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setOperationAction(ISD::SRL, MVT::v8i32, Custom);
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setOperationAction(ISD::SHL, MVT::v4i64, Custom);
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setOperationAction(ISD::SHL, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v4i64, Custom);
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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for (auto VT : { MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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}
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// Custom lower several nodes for 256-bit types.
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for (MVT VT : MVT::vector_valuetypes()) {
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@ -1396,23 +1334,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setLoadExtAction(ISD::EXTLOAD, VT, MaskVT, Custom);
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setTruncStoreAction(VT, MaskVT, Custom);
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}
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setOperationAction(ISD::FADD, MVT::v16f32, Legal);
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setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
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setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
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setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
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setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
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setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
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setOperationAction(ISD::FABS, MVT::v16f32, Custom);
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setOperationAction(ISD::FADD, MVT::v8f64, Legal);
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setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
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setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
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setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
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setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
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setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
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setOperationAction(ISD::FABS, MVT::v8f64, Custom);
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setOperationAction(ISD::FMA, MVT::v8f64, Legal);
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setOperationAction(ISD::FMA, MVT::v16f32, Legal);
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for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
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setOperationAction(ISD::FADD, VT, Legal);
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setOperationAction(ISD::FSUB, VT, Legal);
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setOperationAction(ISD::FMUL, VT, Legal);
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setOperationAction(ISD::FDIV, VT, Legal);
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setOperationAction(ISD::FSQRT, VT, Legal);
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setOperationAction(ISD::FNEG, VT, Custom);
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setOperationAction(ISD::FABS, VT, Custom);
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setOperationAction(ISD::FMA, VT, Legal);
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}
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setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
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@ -1503,16 +1435,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
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}
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setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
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setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
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setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
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for (auto VT : { MVT::v16f32, MVT::v8f64 }) {
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setOperationAction(ISD::FFLOOR, VT, Legal);
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setOperationAction(ISD::FCEIL, VT, Legal);
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setOperationAction(ISD::FTRUNC, VT, Legal);
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setOperationAction(ISD::FRINT, VT, Legal);
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setOperationAction(ISD::FNEARBYINT, VT, Legal);
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}
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
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