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Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 

consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
This commit is contained in:
Alkis Evlogimenos 2004-02-27 06:57:05 +00:00
parent 524ee2beee
commit f020dfb43c
2 changed files with 28 additions and 25 deletions
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24
llvm/lib/Target/X86/InstSelectSimple.cpp
View File

@ -1776,17 +1776,17 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
unsigned Class = getClass (ResultTy);
static const unsigned ConstantOperand[][4] = {
{ X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDri32 }, // SHR
{ X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDri32 }, // SAR
{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SHL
{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SAL = SHL
{ X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDrri32 }, // SHR
{ X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDrri32 }, // SAR
{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrri32 }, // SHL
{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrri32 }, // SAL = SHL
};
static const unsigned NonConstantOperand[][4] = {
{ X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
{ X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
{ X86::SHRrCL8, X86::SHRrCL16, X86::SHRrCL32 }, // SHR
{ X86::SARrCL8, X86::SARrCL16, X86::SARrCL32 }, // SAR
{ X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SHL
{ X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SAL = SHL
};
// Longs, as usual, are handled specially...
@ -1842,9 +1842,9 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
if (isLeftShift) {
// TmpReg2 = shld inHi, inLo
BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
BMI(MBB, IP, X86::SHLDrrCL32,2,TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
// TmpReg3 = shl inLo, CL
BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
BMI(MBB, IP, X86::SHLrCL32, 1, TmpReg3).addReg(SrcReg);
// Set the flags to indicate whether the shift was by more than 32 bits.
BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
@ -1857,9 +1857,9 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
DestReg).addReg(TmpReg3).addReg(TmpReg);
} else {
// TmpReg2 = shrd inLo, inHi
BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
BMI(MBB, IP, X86::SHRDrrCL32,2,TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
// TmpReg3 = s[ah]r inHi, CL
BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
BMI(MBB, IP, isSigned ? X86::SARrCL32 : X86::SHRrCL32, 1, TmpReg3)
.addReg(SrcReg+1);
// Set the flags to indicate whether the shift was by more than 32 bits.

29
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -452,29 +452,32 @@ def TESTmi32 : X86Inst<"test", 0xF7, MRMS0m , Arg32>; // flags = [me
// Shift instructions
class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
def SHLrr8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
def SHLrr16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
def SHLrr32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
def SHLrCL8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
def SHLrCL16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
def SHLrCL32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
def SHLri8 : I2A8 <"shl", 0xC0, MRMS4r >; // R8 <<= imm8
def SHLri16 : I2A8 <"shl", 0xC1, MRMS4r >, OpSize; // R16 <<= imm16
def SHLri32 : I2A8 <"shl", 0xC1, MRMS4r >; // R32 <<= imm32
def SHRrr8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
def SHRrr16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
def SHRrr32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
def SHRrCL8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
def SHRrCL16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
def SHRrCL32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
def SHRri8 : I2A8 <"shr", 0xC0, MRMS5r >; // R8 >>= imm8
def SHRri16 : I2A8 <"shr", 0xC1, MRMS5r >, OpSize; // R16 >>= imm16
def SHRri32 : I2A8 <"shr", 0xC1, MRMS5r >; // R32 >>= imm32
def SARrr8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
def SARrr16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
def SARrr32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
def SARrCL8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
def SARrCL16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
def SARrCL32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
def SARri8 : I2A8 <"sar", 0xC0, MRMS7r >; // R8 >>>= imm8
def SARri16 : I2A8 <"sar", 0xC1, MRMS7r >, OpSize; // R16 >>>= imm16
def SARri32 : I2A8 <"sar", 0xC1, MRMS7r >; // R32 >>>= imm32
def SHLDrr32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
def SHLDri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
def SHRDrr32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
def SHRDri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
def SHLDrri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
def SHRDrrCL32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
def SHRDrri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
// Condition code ops, incl. set if equal/not equal/...
def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH