forked from OSchip/llvm-project
[X86] Remove unused argument from a helper function. NFC
llvm-svn: 372301
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c36b0bf310
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@ -2492,7 +2492,7 @@ static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
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/// Breaks v64i1 value into two registers and adds the new node to the DAG
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static void Passv64i1ArgInRegs(
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const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
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const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
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SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
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CCValAssign &NextVA, const X86Subtarget &Subtarget) {
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assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
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@ -2626,7 +2626,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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assert(VA.getValVT() == MVT::v64i1 &&
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"Currently the only custom case is when we split v64i1 to 2 regs");
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Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I],
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Passv64i1ArgInRegs(dl, DAG, ValToCopy, RegsToPass, VA, RVLocs[++I],
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Subtarget);
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assert(2 == RegsToPass.size() &&
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@ -3875,8 +3875,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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assert(VA.getValVT() == MVT::v64i1 &&
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"Currently the only custom case is when we split v64i1 to 2 regs");
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// Split v64i1 value into two registers
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Passv64i1ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++I],
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Subtarget);
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Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
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} else if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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const TargetOptions &Options = DAG.getTarget().Options;
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