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[X86] Remove unused argument from a helper function. NFC 

llvm-svn: 372301
This commit is contained in:
Craig Topper 2019-09-19 06:27:07 +00:00
parent c36b0bf310
commit eff4fd6999
1 changed files with 3 additions and 4 deletions
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7
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -2492,7 +2492,7 @@ static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
/// Breaks v64i1 value into two registers and adds the new node to the DAG /// Breaks v64i1 value into two registers and adds the new node to the DAG
static void Passv64i1ArgInRegs( static void Passv64i1ArgInRegs(
const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
CCValAssign &NextVA, const X86Subtarget &Subtarget) { CCValAssign &NextVA, const X86Subtarget &Subtarget) {
assert(Subtarget.hasBWI() && "Expected AVX512BW target!"); assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
@ -2626,7 +2626,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
assert(VA.getValVT() == MVT::v64i1 && assert(VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"); "Currently the only custom case is when we split v64i1 to 2 regs");
Passv64i1ArgInRegs(dl, DAG, Chain, ValToCopy, RegsToPass, VA, RVLocs[++I], Passv64i1ArgInRegs(dl, DAG, ValToCopy, RegsToPass, VA, RVLocs[++I],
Subtarget); Subtarget);
assert(2 == RegsToPass.size() && assert(2 == RegsToPass.size() &&
@ -3875,8 +3875,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
assert(VA.getValVT() == MVT::v64i1 && assert(VA.getValVT() == MVT::v64i1 &&
"Currently the only custom case is when we split v64i1 to 2 regs"); "Currently the only custom case is when we split v64i1 to 2 regs");
// Split v64i1 value into two registers // Split v64i1 value into two registers
Passv64i1ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++I], Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
Subtarget);
} else if (VA.isRegLoc()) { } else if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
const TargetOptions &Options = DAG.getTarget().Options; const TargetOptions &Options = DAG.getTarget().Options;