forked from OSchip/llvm-project
Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion
See bug https://bugs.llvm.org/show_bug.cgi?id=35631 r318704 is giving a fatal error on some code with unsigned to floating point conversions. llvm-svn: 320429
This commit is contained in:
Richard Trieu
parent
fc1a912b9b
commit
efef032f02
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@ -1559,6 +1559,9 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::BITCAST, MVT::f32, Expand);
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setOperationAction(ISD::BITCAST, MVT::i32, Expand);
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// Sparc has no select or setcc: expand to SELECT_CC.
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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@ -1587,14 +1590,13 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
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setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
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setOperationAction(ISD::BITCAST, MVT::i32, Custom);
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setOperationAction(ISD::BITCAST, MVT::f32, Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::ADDC, MVT::i64, Custom);
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setOperationAction(ISD::ADDE, MVT::i64, Custom);
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setOperationAction(ISD::SUBC, MVT::i64, Custom);
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setOperationAction(ISD::SUBE, MVT::i64, Custom);
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setOperationAction(ISD::BITCAST, MVT::f64, Expand);
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setOperationAction(ISD::BITCAST, MVT::i64, Expand);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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@ -1608,9 +1610,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::ROTL , MVT::i64, Expand);
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setOperationAction(ISD::ROTR , MVT::i64, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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setOperationAction(ISD::BITCAST, MVT::i64, Custom);
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setOperationAction(ISD::BITCAST, MVT::f64, Custom);
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}
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// ATOMICs.
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@ -2426,76 +2425,23 @@ static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
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1);
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}
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SDValue SparcTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
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SDLoc dl(Op);
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EVT SrcVT = Op.getOperand(0).getValueType();
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EVT DstVT = Op.getValueType();
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if (Subtarget->isVIS3()) {
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if (DstVT == MVT::f32 && SrcVT == MVT::i32) {
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return Op; // Legal
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} else if (DstVT == MVT::f64 && SrcVT == MVT::i64) {
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return (Subtarget->is64Bit())
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? Op
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: SDValue(); // Legal on 64 bit, otherwise Expand
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} else if (DstVT == MVT::i64 && SrcVT == MVT::f64) {
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return (Subtarget->is64Bit())
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? Op
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: SDValue(); // Legal on 64 bit, otherwise Expand
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}
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}
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// Expand
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return SDValue();
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}
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SDValue SparcTargetLowering::LowerUINT_TO_FP(SDValue Op,
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SelectionDAG &DAG) const {
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static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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EVT OpVT = Op.getOperand(0).getValueType();
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assert(OpVT == MVT::i32 || OpVT == MVT::i64);
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// Expand f128 operations to fp128 ABI calls.
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if (Op.getValueType() == MVT::f128 &&
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(!Subtarget->hasHardQuad() || !isTypeLegal(OpVT))) {
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return LowerF128Op(Op, DAG,
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getLibcallName(OpVT == MVT::i32
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? RTLIB::UINTTOFP_I32_F128
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: RTLIB::UINTTOFP_I64_F128),
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1);
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}
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// Expand if it does not involve f128 or the target has support for
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// quad floating point instructions and the operand type is legal.
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if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
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return SDValue();
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// Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
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// optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
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// the optimization here.
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if (DAG.SignBitIsZero(Op.getOperand(0))) {
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EVT floatVT = MVT::f32;
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unsigned IntToFloatOpcode = SPISD::ITOF;
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if (OpVT == MVT::i64) {
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floatVT = MVT::f64;
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IntToFloatOpcode = SPISD::XTOF;
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}
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// Convert the int value to FP in an FP register.
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SDValue FloatTmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
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return DAG.getNode(IntToFloatOpcode, dl, Op.getValueType(), FloatTmp);
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}
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if (OpVT == MVT::i32 && Subtarget->is64Bit()) {
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SDValue Int64Tmp =
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DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Op.getOperand(0));
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SDValue Float64Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Int64Tmp);
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return DAG.getNode(SPISD::XTOF, dl, Op.getValueType(), Float64Tmp);
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}
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return SDValue();
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(OpVT == MVT::i32
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? RTLIB::UINTTOFP_I32_F128
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: RTLIB::UINTTOFP_I64_F128),
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1);
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}
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static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
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@ -3113,7 +3059,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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hasHardQuad);
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case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
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hasHardQuad);
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case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
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case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
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hasHardQuad);
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case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
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hasHardQuad);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
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@ -3150,7 +3097,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ATOMIC_LOAD:
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case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::BITCAST: return LowerBITCAST(Op, DAG);
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}
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}
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@ -192,10 +192,6 @@ namespace llvm {
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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bool ShouldShrinkFPConstant(EVT VT) const override {
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// Do not shrink FP constpool if VT == MVT::f128.
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// (ldd, call _Q_fdtoq) is more expensive than two ldds.
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@ -243,21 +243,16 @@ def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
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(ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
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let rs1 = 0 in {
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def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd), (ins FPRegs:$rs2),
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"movstosw $rs2, $rd",
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[(set I64Regs:$rd, (sext (i32 (bitconvert FPRegs:$rs2))))]>;
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def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd), (ins FPRegs:$rs2),
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"movstouw $rs2, $rd",
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[(set I64Regs:$rd, (zext (i32 (bitconvert FPRegs:$rs2))))]>;
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def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd), (ins DFPRegs:$rs2),
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"movdtox $rs2, $rd",
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[(set I64Regs:$rd, (bitconvert DFPRegs:$rs2))]>;
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def MOVWTOS : VISInstFormat<0b100011001, (outs FPRegs:$rd), (ins IntRegs:$rs2),
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"movwtos $rs2, $rd",
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[(set FPRegs:$rd, (bitconvert i32:$rs2))]>;
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def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd), (ins I64Regs:$rs2),
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"movxtod $rs2, $rd",
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[(set DFPRegs:$rd, (bitconvert I64Regs:$rs2))]>;
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def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
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(ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
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def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
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(ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
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def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
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(ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
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def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd),
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(ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
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def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
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(ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
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}
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def PDISTN : VISInst<0b000111111, "pdistn">;
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@ -3,8 +3,6 @@
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; RUN: llc -march=sparc -O0 < %s | FileCheck %s -check-prefix=V8-UNOPT
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; RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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; RUN: llc -mtriple=sparc64-unknown-linux < %s | FileCheck %s -check-prefix=SPARC64
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; RUN: llc -march=sparc -mcpu=niagara4 < %s | FileCheck %s -check-prefix=VIS3
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; RUN: llc -march=sparcv9 -mcpu=niagara4 < %s | FileCheck %s -check-prefix=VIS3-64
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; V8-LABEL: test_neg:
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; V8: call get_double
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@ -196,7 +194,7 @@ entry:
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; V9: fstoi
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; SPARC64-LABEL: test_utos_stou
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; SPARC64: fxtos
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; SPARC64: fdtos
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; SPARC64: fstoi
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define void @test_utos_stou(i32 %a, i32* %ptr0, float* %ptr1) {
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@ -242,9 +240,6 @@ entry:
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; SPARC64-NOT: fitod
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; SPARC64: fdtoi
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; VIS3-64-LABEL: test_utod_dtou
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; VIS3-64: movxtod
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define void @test_utod_dtou(i32 %a, double %b, i32* %ptr0, double* %ptr1) {
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entry:
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%0 = uitofp i32 %a to double
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@ -253,49 +248,3 @@ entry:
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store i32 %1, i32* %ptr0, align 8
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ret void
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}
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; V8-LABEL: test_ustod
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; V8: fitod
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; VIS3-LABEL: test_ustod
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; VIS3: movwtos
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define double @test_ustod(i16 zeroext) {
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%2 = uitofp i16 %0 to double
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ret double %2
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}
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; V8-LABEL: test_ustos
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; V8: fitos
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; VIS3-LABEL: test_ustos
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; VIS3: movwtos
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define float @test_ustos(i16 zeroext) {
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%2 = uitofp i16 %0 to float
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ret float %2
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}
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; check for movwtos used for bitcast
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;
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; VIS3-LABEL: test_bitcast_utos
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; VIS3:movwtos
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define float @test_bitcast_utos(i32 ) {
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%2 = bitcast i32 %0 to float
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ret float %2
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}
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; check for movxtod used for bitcast
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;
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; VIS3-64-LABEL: test_bitcast_uxtod
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; VIS3-64:movxtod
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define double @test_bitcast_uxtod(i64 ) {
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%2 = bitcast i64 %0 to double
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ret double %2
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}
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