forked from OSchip/llvm-project
[X86][SSE] Add srem x, (1 << c) combine tests
Now that D45806 has landed we can start trying to avoid scalarizing srem by constant - these tests demonstrate some example cases. llvm-svn: 336360
This commit is contained in:
Simon Pilgrim
parent
061af9aafa
commit
efe84b9d12
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@ -132,6 +132,233 @@ define <4 x i32> @combine_vec_srem_by_pos1(<4 x i32> %x) {
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ret <4 x i32> %2
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}
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; fold (srem x, (1 << c)) -> x - (x / (1 << c)) * (1 << c).
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define <4 x i32> @combine_vec_srem_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $30, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: pand {{.*}}(%rip), %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_srem_by_pow2a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_srem_by_pow2a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX2-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967292,4294967292,4294967292,4294967292]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_srem_by_pow2a_neg(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2a_neg:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $30, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: psrad $2, %xmm1
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pxor %xmm3, %xmm3
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; SSE-NEXT: psubd %xmm1, %xmm3
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; SSE-NEXT: pslld $2, %xmm3
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; SSE-NEXT: psubd %xmm3, %xmm2
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; SSE-NEXT: psubd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_pow2a_neg:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpsrad $2, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpslld $2, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 -4, i32 -4, i32 -4, i32 -4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: extractps $3, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $29, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: andl $-8, %ecx
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; SSE-NEXT: subl %ecx, %eax
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: extractps $2, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $30, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: andl $-4, %ecx
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; SSE-NEXT: subl %ecx, %eax
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; SSE-NEXT: movd %eax, %xmm2
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; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; SSE-NEXT: extractps $1, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: shrl $31, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: andl $-2, %ecx
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; SSE-NEXT: subl %ecx, %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_pow2b:
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; AVX: # %bb.0:
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; AVX-NEXT: vextractps $3, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $29, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: andl $-8, %ecx
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; AVX-NEXT: subl %ecx, %eax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vextractps $2, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $30, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: andl $-4, %ecx
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; AVX-NEXT: subl %ecx, %eax
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; AVX-NEXT: vmovd %eax, %xmm2
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; AVX-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; AVX-NEXT: vextractps $1, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: shrl $31, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: andl $-2, %ecx
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; AVX-NEXT: subl %ecx, %eax
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; AVX-NEXT: vmovd %eax, %xmm0
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1]
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 1, i32 2, i32 4, i32 8>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2b_neg:
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; SSE: # %bb.0:
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $30, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: shrl $2, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: shll $2, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: subl %ecx, %eax
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; SSE-NEXT: movd %xmm0, %ecx
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; SSE-NEXT: movl %ecx, %edx
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; SSE-NEXT: shrl $31, %edx
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; SSE-NEXT: addl %ecx, %edx
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; SSE-NEXT: shrl %edx
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; SSE-NEXT: negl %edx
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; SSE-NEXT: addl %edx, %edx
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; SSE-NEXT: negl %edx
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; SSE-NEXT: subl %edx, %ecx
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; SSE-NEXT: movd %ecx, %xmm1
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; SSE-NEXT: pinsrd $1, %eax, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $29, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: shrl $3, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: shll $3, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: subl %ecx, %eax
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; SSE-NEXT: pinsrd $2, %eax, %xmm1
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $28, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: shrl $4, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: shll $4, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: subl %ecx, %eax
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; SSE-NEXT: pinsrd $3, %eax, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_pow2b_neg:
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; AVX: # %bb.0:
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $30, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: shrl $2, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: shll $2, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: subl %ecx, %eax
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; AVX-NEXT: vmovd %xmm0, %ecx
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; AVX-NEXT: movl %ecx, %edx
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; AVX-NEXT: shrl $31, %edx
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; AVX-NEXT: addl %ecx, %edx
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; AVX-NEXT: shrl %edx
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; AVX-NEXT: negl %edx
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; AVX-NEXT: addl %edx, %edx
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; AVX-NEXT: negl %edx
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; AVX-NEXT: subl %edx, %ecx
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; AVX-NEXT: vmovd %ecx, %xmm1
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; AVX-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $29, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: shrl $3, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: shll $3, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: subl %ecx, %eax
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; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $28, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: shrl $4, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: shll $4, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: subl %ecx, %eax
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; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 -2, i32 -4, i32 -8, i32 -16>
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ret <4 x i32> %1
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}
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; OSS-Fuzz #6883
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; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6883
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define i32 @ossfuzz6883() {
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