forked from OSchip/llvm-project
[AVR] Add the machine code backend
Summary: This adds the AVR machine code backend (`AVRAsmBackend.cpp`). This will allow us to generate machine code from assembled AVR instructions. Reviewers: arsenm, kparzysz Subscribers: modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25029 llvm-svn: 283297
This commit is contained in:
Dylan McKay
parent
27358cff88
commit
efe40389c0
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//===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AVRAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AVRAsmBackend.h"
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#include "MCTargetDesc/AVRFixupKinds.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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// FIXME: we should be doing checks to make sure asm operands
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// are not out of bounds.
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namespace adjust {
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using namespace llvm;
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void signed_width(unsigned Width, uint64_t Value, std::string Description,
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const MCFixup &Fixup, MCContext *Ctx = nullptr) {
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if (!isIntN(Width, Value)) {
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std::string Diagnostic = "out of range " + Description;
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int64_t Min = minIntN(Width);
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int64_t Max = maxIntN(Width);
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Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
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" to " + std::to_string(Max) + ")";
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if (Ctx) {
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Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
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} else {
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llvm_unreachable(Diagnostic.c_str());
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}
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}
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}
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void unsigned_width(unsigned Width, uint64_t Value, std::string Description,
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const MCFixup &Fixup, MCContext *Ctx = nullptr) {
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if (!isUIntN(Width, Value)) {
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std::string Diagnostic = "out of range " + Description;
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int64_t Max = maxUIntN(Width);
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Diagnostic += " (expected an integer in the range 0 to " +
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std::to_string(Max) + ")";
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if (Ctx) {
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Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
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} else {
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llvm_unreachable(Diagnostic.c_str());
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}
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}
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}
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/// Adjusts the value of a branch target before fixup application.
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void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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// We have one extra bit of precision because the value is rightshifted by
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// one.
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unsigned_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
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// Rightshifts the value by one.
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AVR::fixups::adjustBranchTarget(Value);
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}
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/// Adjusts the value of a relative branch target before fixup application.
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void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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// We have one extra bit of precision because the value is rightshifted by
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// one.
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signed_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
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Value -= 2;
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// Rightshifts the value by one.
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AVR::fixups::adjustBranchTarget(Value);
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}
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/// 22-bit absolute fixup.
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///
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/// Resolves to:
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/// 1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
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///
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/// Offset of 0 (so the result is left shifted by 3 bits before application).
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void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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adjustBranch(Size, Fixup, Value, Ctx);
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auto top = Value & (0xf00000 << 6); // the top four bits
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auto middle = Value & (0x1ffff << 5); // the middle 13 bits
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auto bottom = Value & 0x1f; // end bottom 5 bits
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Value = (top << 6) | (middle << 3) | (bottom << 0);
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}
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/// 7-bit PC-relative fixup.
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///
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/// Resolves to:
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/// 0000 00kk kkkk k000
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/// Offset of 0 (so the result is left shifted by 3 bits before application).
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void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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adjustRelativeBranch(Size, Fixup, Value, Ctx);
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// Because the value may be negative, we must mask out the sign bits
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Value &= 0x7f;
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}
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/// 12-bit PC-relative fixup.
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/// Yes, the fixup is 12 bits even though the name says otherwise.
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///
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/// Resolves to:
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/// 0000 kkkk kkkk kkkk
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/// Offset of 0 (so the result isn't left-shifted before application).
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void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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adjustRelativeBranch(Size, Fixup, Value, Ctx);
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// Because the value may be negative, we must mask out the sign bits
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Value &= 0xfff;
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}
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/// 6-bit fixup for the immediate operand of the ADIW family of
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/// instructions.
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///
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/// Resolves to:
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/// 0000 0000 kk00 kkkk
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void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
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Value = ((Value & 0x30) << 2) | (Value & 0x0f);
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}
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/// 5-bit port number fixup on the SBIC family of instructions.
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///
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/// Resolves to:
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/// 0000 0000 AAAA A000
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void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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unsigned_width(5, Value, std::string("port number"), Fixup, Ctx);
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Value &= 0x1f;
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Value <<= 3;
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}
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/// 6-bit port number fixup on the `IN` family of instructions.
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///
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/// Resolves to:
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/// 1011 0AAd dddd AAAA
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void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
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Value = ((Value & 0x30) << 5) | (Value & 0x0f);
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}
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/// Adjusts a program memory address.
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/// This is a simple right-shift.
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void pm(uint64_t &Value) {
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Value >>= 1;
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}
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/// Fixups relating to the LDI instruction.
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namespace ldi {
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/// Adjusts a value to fix up the immediate of an `LDI Rd, K` instruction.
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///
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/// Resolves to:
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/// 0000 KKKK 0000 KKKK
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/// Offset of 0 (so the result isn't left-shifted before application).
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void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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uint64_t upper = Value & 0xf0;
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uint64_t lower = Value & 0x0f;
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Value = (upper << 4) | lower;
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}
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void neg(uint64_t &Value) { Value *= -1; }
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void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value &= 0xff;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value = (Value & 0xff00) >> 8;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value = (Value & 0xff0000) >> 16;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value = (Value & 0xff000000) >> 24;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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} // end of ldi namespace
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} // end of adjust namespace
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namespace llvm {
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// Prepare value for the target space for it
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void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx) const {
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// The size of the fixup in bits.
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uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
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unsigned Kind = Fixup.getKind();
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switch (Kind) {
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default:
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llvm_unreachable("unhandled fixup");
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case AVR::fixup_7_pcrel:
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adjust::fixup_7_pcrel(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_13_pcrel:
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adjust::fixup_13_pcrel(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_call:
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adjust::fixup_call(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_ldi:
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adjust::ldi::fixup(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_lo8_ldi:
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case AVR::fixup_lo8_ldi_pm:
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if (Kind == AVR::fixup_lo8_ldi_pm) adjust::pm(Value);
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adjust::ldi::lo8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hi8_ldi:
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case AVR::fixup_hi8_ldi_pm:
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if (Kind == AVR::fixup_hi8_ldi_pm) adjust::pm(Value);
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adjust::ldi::hi8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hh8_ldi:
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case AVR::fixup_hh8_ldi_pm:
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if (Kind == AVR::fixup_hh8_ldi_pm) adjust::pm(Value);
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adjust::ldi::hh8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_ms8_ldi:
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adjust::ldi::ms8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_lo8_ldi_neg:
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case AVR::fixup_lo8_ldi_pm_neg:
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if (Kind == AVR::fixup_lo8_ldi_pm_neg) adjust::pm(Value);
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adjust::ldi::neg(Value);
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adjust::ldi::lo8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hi8_ldi_neg:
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case AVR::fixup_hi8_ldi_pm_neg:
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if (Kind == AVR::fixup_hi8_ldi_pm_neg) adjust::pm(Value);
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adjust::ldi::neg(Value);
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adjust::ldi::hi8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hh8_ldi_neg:
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case AVR::fixup_hh8_ldi_pm_neg:
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if (Kind == AVR::fixup_hh8_ldi_pm_neg) adjust::pm(Value);
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adjust::ldi::neg(Value);
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adjust::ldi::hh8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_ms8_ldi_neg:
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adjust::ldi::neg(Value);
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adjust::ldi::ms8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_16:
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adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
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Value &= 0xffff;
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break;
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case AVR::fixup_6_adiw:
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adjust::fixup_6_adiw(Fixup, Value, Ctx);
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break;
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case AVR::fixup_port5:
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adjust::fixup_port5(Fixup, Value, Ctx);
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break;
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case AVR::fixup_port6:
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adjust::fixup_port6(Fixup, Value, Ctx);
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break;
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// Fixups which do not require adjustments.
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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break;
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case FK_GPRel_4:
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llvm_unreachable("don't know how to adjust this fixup");
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break;
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}
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}
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MCObjectWriter *AVRAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
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return createAVRELFObjectWriter(OS,
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MCELFObjectTargetWriter::getOSABI(OSType));
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}
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void AVRAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value,
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bool IsPCRel) const {
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if (Value == 0)
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return; // Doesn't change encoding.
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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// The number of bits in the fixup mask
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auto NumBits = Info.TargetSize + Info.TargetOffset;
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auto NumBytes = (NumBits / 8) + ((NumBits % 8) == 0 ? 0 : 1);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned i = 0; i < NumBytes; ++i) {
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uint8_t mask = (((Value >> (i * 8)) & 0xff));
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Data[Offset + i] |= mask;
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}
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}
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MCFixupKindInfo const &AVRAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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// NOTE: Many AVR fixups work on sets of non-contignous bits. We work around
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// this by saying that the fixup is the size of the entire instruction.
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const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// AVRFixupKinds.h.
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//
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// name offset bits flags
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{"fixup_32", 0, 32, 0},
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{"fixup_7_pcrel", 3, 7, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_13_pcrel", 0, 12, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_16", 0, 16, 0},
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{"fixup_16_pm", 0, 16, 0},
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{"fixup_ldi", 0, 8, 0},
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{"fixup_lo8_ldi", 0, 8, 0},
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{"fixup_hi8_ldi", 0, 8, 0},
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{"fixup_hh8_ldi", 0, 8, 0},
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{"fixup_ms8_ldi", 0, 8, 0},
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{"fixup_lo8_ldi_neg", 0, 8, 0},
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{"fixup_hi8_ldi_neg", 0, 8, 0},
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{"fixup_hh8_ldi_neg", 0, 8, 0},
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{"fixup_ms8_ldi_neg", 0, 8, 0},
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{"fixup_lo8_ldi_pm", 0, 8, 0},
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{"fixup_hi8_ldi_pm", 0, 8, 0},
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{"fixup_hh8_ldi_pm", 0, 8, 0},
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{"fixup_lo8_ldi_pm_neg", 0, 8, 0},
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{"fixup_hi8_ldi_pm_neg", 0, 8, 0},
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{"fixup_hh8_ldi_pm_neg", 0, 8, 0},
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{"fixup_call", 0, 22, 0},
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{"fixup_6", 0, 16, 0}, // non-contiguous
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{"fixup_6_adiw", 0, 6, 0},
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{"fixup_lo8_ldi_gs", 0, 8, 0},
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{"fixup_hi8_ldi_gs", 0, 8, 0},
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{"fixup_8", 0, 8, 0},
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{"fixup_8_lo8", 0, 8, 0},
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{"fixup_8_hi8", 0, 8, 0},
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{"fixup_8_hlo8", 0, 8, 0},
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{"fixup_sym_diff", 0, 32, 0},
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{"fixup_16_ldst", 0, 16, 0},
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{"fixup_lds_sts_16", 0, 16, 0},
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{"fixup_port6", 0, 16, 0}, // non-contiguous
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{"fixup_port5", 3, 5, 0},
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool AVRAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// If the count is not 2-byte aligned, we must be writing data into the text
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// section (otherwise we have unaligned instructions, and thus have far
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// bigger problems), so just write zeros instead.
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assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
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OW->WriteZeros(Count);
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return true;
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}
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void AVRAsmBackend::processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup,
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const MCFragment *DF,
|
||||
const MCValue &Target, uint64_t &Value,
|
||||
bool &IsResolved) {
|
||||
switch ((unsigned) Fixup.getKind()) {
|
||||
// Fixups which should always be recorded as relocations.
|
||||
case AVR::fixup_7_pcrel:
|
||||
case AVR::fixup_13_pcrel:
|
||||
case AVR::fixup_call:
|
||||
IsResolved = false;
|
||||
break;
|
||||
default:
|
||||
// Parsed LLVM-generated temporary labels are already
|
||||
// adjusted for instruction size, but normal labels aren't.
|
||||
//
|
||||
// To handle both cases, we simply un-adjust the temporary label
|
||||
// case so it acts like all other labels.
|
||||
if (Target.getSymA()->getSymbol().isTemporary())
|
||||
Value += 2;
|
||||
|
||||
adjustFixupValue(Fixup, Value, &Asm.getContext());
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
MCAsmBackend *createAVRAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
||||
const Triple &TT, StringRef CPU,
|
||||
const llvm::MCTargetOptions &TO) {
|
||||
return new AVRAsmBackend(TT.getOS());
|
||||
}
|
||||
|
||||
} // end of namespace llvm
|
||||
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
//===-- AVRAsmBackend.h - AVR Asm Backend --------------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// \file The AVR assembly backend implementation.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
|
||||
#ifndef LLVM_AVR_ASM_BACKEND_H
|
||||
#define LLVM_AVR_ASM_BACKEND_H
|
||||
|
||||
#include "MCTargetDesc/AVRFixupKinds.h"
|
||||
|
||||
#include "llvm/ADT/Triple.h"
|
||||
#include "llvm/MC/MCAsmBackend.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MCAssembler;
|
||||
class MCObjectWriter;
|
||||
class Target;
|
||||
|
||||
struct MCFixupKindInfo;
|
||||
|
||||
/// Utilities for manipulating generated AVR machine code.
|
||||
class AVRAsmBackend : public MCAsmBackend {
|
||||
public:
|
||||
|
||||
AVRAsmBackend(Triple::OSType OSType)
|
||||
: MCAsmBackend(), OSType(OSType) {}
|
||||
|
||||
void adjustFixupValue(const MCFixup &Fixup, uint64_t &Value,
|
||||
MCContext *Ctx = nullptr) const;
|
||||
|
||||
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
|
||||
|
||||
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
|
||||
uint64_t Value, bool IsPCRel) const override;
|
||||
|
||||
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
|
||||
|
||||
unsigned getNumFixupKinds() const override {
|
||||
return AVR::NumTargetFixupKinds;
|
||||
}
|
||||
|
||||
bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
|
||||
|
||||
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
|
||||
const MCRelaxableFragment *DF,
|
||||
const MCAsmLayout &Layout) const override {
|
||||
llvm_unreachable("RelaxInstruction() unimplemented");
|
||||
return false;
|
||||
}
|
||||
|
||||
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
|
||||
MCInst &Res) const override {}
|
||||
|
||||
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
|
||||
|
||||
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
|
||||
const MCFixup &Fixup, const MCFragment *DF,
|
||||
const MCValue &Target, uint64_t &Value,
|
||||
bool &IsResolved) override;
|
||||
|
||||
private:
|
||||
Triple::OSType OSType;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_AVR_ASM_BACKEND_H
|
||||
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
add_llvm_library(LLVMAVRDesc
|
||||
AVRAsmBackend.cpp
|
||||
AVRELFObjectWriter.cpp
|
||||
AVRELFStreamer.cpp
|
||||
AVRMCAsmInfo.cpp
|
||||
|
|
|
|||
Loading…
Reference in New Issue