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[AArch64] Add v8.5-a Memory Tagging GMID_EL1 register 

The latest version of the MTE spec added a system
register 'GMID_EL1'. It contains the block size used
by the LDGM and STGM instructions and is read only.

The specification can be found here:
https://developer.arm.com/docs/ddi0596/c

llvm-svn: 357392
This commit is contained in:
David Spickett 2019-04-01 14:41:14 +00:00
parent 30c2f20e55
commit efe376add6
4 changed files with 32 additions and 0 deletions
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1
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -1457,6 +1457,7 @@ def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0110, 0b0101, 0b000>;
def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0110, 0b0110, 0b000>;
def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0110, 0b0110, 0b000>;
def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0110, 0b0110, 0b001>;
def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>;
} // HasMTE
// Cyclone specific system registers

20
llvm/test/MC/AArch64/armv8.5a-mte-error.s
View File

@ -553,6 +553,7 @@ mrs tfsr_el2
mrs tfsr_el3
mrs tfsr_el12
mrs tfsre0_el1
mrs gmid_el1
// CHECK: invalid operand for instruction
// CHECK-NEXT: tco
@ -570,6 +571,8 @@ mrs tfsre0_el1
// CHECK-NEXT: tfsr_el12
// CHECK: invalid operand for instruction
// CHECK-NEXT: tfsre0_el1
// CHECK: invalid operand for instruction
// CHECK-NEXT: gmid_el1
mrs tco, #0
mrs tco, x0
@ -580,6 +583,7 @@ mrs tfsr_el2, x4
mrs tfsr_el3, x5
mrs tfsr_el12, x6
mrs tfsre0_el1, x7
mrs gmid_el1, x7
// CHECK: invalid operand for instruction
// CHECK-NEXT: tco, #0
@ -599,6 +603,8 @@ mrs tfsre0_el1, x7
// CHECK-NEXT: tfsr_el12
// CHECK: invalid operand for instruction
// CHECK-NEXT: tfsre0_el1
// CHECK: invalid operand for instruction
// CHECK-NEXT: gmid_el1
msr tco
msr gcr_el1
@ -608,6 +614,7 @@ msr tfsr_el2
msr tfsr_el3
msr tfsr_el12
msr tfsre0_el1
msr gmid_el1
// CHECK: too few operands for instruction
// CHECK-NEXT: tco
@ -625,6 +632,8 @@ msr tfsre0_el1
// CHECK-NEXT: tfsr_el12
// CHECK: too few operands for instruction
// CHECK-NEXT: tfsre0_el1
// CHECK: expected writable system register or pstate
// CHECK-NEXT: gmid_el1
msr x0, tco
msr x1, gcr_el1
@ -634,6 +643,7 @@ msr x4, tfsr_el2
msr x5, tfsr_el3
msr x6, tfsr_el12
msr x7, tfsre0_el1
msr x7, gmid_el1
// CHECK: expected writable system register or pstate
// CHECK-NEXT: tco
@ -651,6 +661,13 @@ msr x7, tfsre0_el1
// CHECK-NEXT: tfsr_el12
// CHECK: expected writable system register or pstate
// CHECK-NEXT: tfsre0_el1
// CHECK: expected writable system register or pstate
// CHECK-NEXT: gmid_el1
msr gmid_el1, x7
// CHECK: expected writable system register or pstate
// CHECK-NEXT: gmid_el1
// Among the system registers added by MTE, only TCO can be used with MSR (imm).
// The rest can only be used with MSR (reg).
@ -661,6 +678,7 @@ msr tfsr_el2, #4
msr tfsr_el3, #5
msr tfsr_el12, #6
msr tfsre0_el1, #7
msr gmid_el1, #7
// CHECK: invalid operand for instruction
// CHECK-NEXT: gcr_el1
@ -676,6 +694,8 @@ msr tfsre0_el1, #7
// CHECK-NEXT: tfsr_el12
// CHECK: invalid operand for instruction
// CHECK-NEXT: tfsre0_el1
// CHECK: expected writable system register or pstate
// CHECK-NEXT: gmid_el1
// Xd cannot be the stack pointer, the rest can
subps sp, x0, x1

4
llvm/test/MC/AArch64/armv8.5a-mte.s
View File

@ -420,6 +420,7 @@ mrs x4, tfsr_el2
mrs x5, tfsr_el3
mrs x6, tfsr_el12
mrs x7, tfsre0_el1
mrs x7, gmid_el1
// CHECK: mrs x0, TCO // encoding: [0xe0,0x42,0x3b,0xd5]
// CHECK: mrs x1, GCR_EL1 // encoding: [0xc1,0x10,0x38,0xd5]
@ -429,6 +430,7 @@ mrs x7, tfsre0_el1
// CHECK: mrs x5, TFSR_EL3 // encoding: [0x05,0x66,0x3e,0xd5]
// CHECK: mrs x6, TFSR_EL12 // encoding: [0x06,0x66,0x3d,0xd5]
// CHECK: mrs x7, TFSRE0_EL1 // encoding: [0x27,0x66,0x38,0xd5]
// CHECK: mrs x7, GMID_EL1 // encoding: [0x87,0x00,0x39,0xd5]
// NOMTE: expected readable system register
// NOMTE-NEXT: tco
@ -446,6 +448,8 @@ mrs x7, tfsre0_el1
// NOMTE-NEXT: tfsr_el12
// NOMTE: expected readable system register
// NOMTE-NEXT: tfsre0_el1
// NOMTE: expected readable system register
// NOMTE-NEXT: gmid_el1
msr tco, #0

7
llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
View File

@ -493,6 +493,7 @@
[0x05,0x66,0x3e,0xd5]
[0x06,0x66,0x3d,0xd5]
[0x27,0x66,0x38,0xd5]
[0x88,0x00,0x39,0xd5]
# CHECK: mrs x0, TCO
# CHECK: mrs x1, GCR_EL1
@ -502,6 +503,7 @@
# CHECK: mrs x5, TFSR_EL3
# CHECK: mrs x6, TFSR_EL12
# CHECK: mrs x7, TFSRE0_EL1
# CHECK: mrs x8, GMID_EL1
# NOMTE: mrs x0, S3_3_C4_C2_7
# NOMTE: mrs x1, S3_0_C1_C0_6
@ -511,6 +513,7 @@
# NOMTE: mrs x5, S3_6_C6_C6_0
# NOMTE: mrs x6, S3_5_C6_C6_0
# NOMTE: mrs x7, S3_0_C6_C6_1
# NOMTE: mrs x8, S3_1_C0_C0_4
[0x9f,0x40,0x03,0xd5]
@ -525,6 +528,7 @@
[0x05,0x66,0x1e,0xd5]
[0x06,0x66,0x1d,0xd5]
[0x27,0x66,0x18,0xd5]
[0x88,0x00,0x19,0xd5]
# CHECK: msr TCO, x0
# CHECK: msr GCR_EL1, x1
@ -534,6 +538,8 @@
# CHECK: msr TFSR_EL3, x5
# CHECK: msr TFSR_EL12, x6
# CHECK: msr TFSRE0_EL1, x7
# GMID_EL1 is read only
# CHECK: msr S3_1_C0_C0_4, x8
# NOMTE: msr S3_3_C4_C2_7, x0
# NOMTE: msr S3_0_C1_C0_6, x1
@ -543,3 +549,4 @@
# NOMTE: msr S3_6_C6_C6_0, x5
# NOMTE: msr S3_5_C6_C6_0, x6
# NOMTE: msr S3_0_C6_C6_1, x7
# NOMTE: msr S3_1_C0_C0_4, x8