forked from OSchip/llvm-project
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton. llvm-svn: 187476
This commit is contained in:
Craig Topper
parent
c3bc8b8de6
commit
efd67d4612
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@ -137,16 +137,11 @@ void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
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}
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}
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static void PrintRegName(raw_ostream &O, StringRef RegName) {
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for (unsigned i = 0, e = RegName.size(); i != e; ++i)
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O << (char)toupper(RegName[i]);
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}
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void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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PrintRegName(O, getRegisterName(Op.getReg()));
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printRegName(O, Op.getReg());
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} else if (Op.isImm()) {
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O << Op.getImm();
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} else {
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@ -41,60 +41,60 @@ public:
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void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "OPAQUE PTR ";
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O << "opaque ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "BYTE PTR ";
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O << "byte ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "WORD PTR ";
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O << "word ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "DWORD PTR ";
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O << "dword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "QWORD PTR ";
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O << "qword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "XMMWORD PTR ";
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O << "xmmword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "YMMWORD PTR ";
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O << "ymmword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "ZMMWORD PTR ";
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O << "zmmword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "DWORD PTR ";
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O << "dword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "QWORD PTR ";
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O << "qword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "XWORD PTR ";
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O << "xword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "XMMWORD PTR ";
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O << "xmmword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "YMMWORD PTR ";
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O << "ymmword ptr ";
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printMemReference(MI, OpNo, O);
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}
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void printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "ZMMWORD PTR ";
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O << "zmmword ptr ";
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printMemReference(MI, OpNo, O);
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}
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};
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@ -1041,13 +1041,13 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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} // Defs = [EFLAGS]
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def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
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"{$src, %al|AL, $src}">;
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"{$src, %al|al, $src}">;
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def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
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"{$src, %ax|AX, $src}">;
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"{$src, %ax|ax, $src}">;
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def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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"{$src, %eax|eax, $src}">;
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def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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"{$src, %rax|rax, $src}">;
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}
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/// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is
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@ -1112,13 +1112,13 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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} // Uses = [EFLAGS], Defs = [EFLAGS]
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def NAME#8i8 : BinOpAI_FF<BaseOpc4, mnemonic, Xi8 , AL,
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"{$src, %al|AL, $src}">;
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"{$src, %al|al, $src}">;
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def NAME#16i16 : BinOpAI_FF<BaseOpc4, mnemonic, Xi16, AX,
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"{$src, %ax|AX, $src}">;
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"{$src, %ax|ax, $src}">;
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def NAME#32i32 : BinOpAI_FF<BaseOpc4, mnemonic, Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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"{$src, %eax|eax, $src}">;
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def NAME#64i32 : BinOpAI_FF<BaseOpc4, mnemonic, Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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"{$src, %rax|rax, $src}">;
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}
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/// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
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@ -1179,13 +1179,13 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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} // Defs = [EFLAGS]
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def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
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"{$src, %al|AL, $src}">;
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"{$src, %al|al, $src}">;
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def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
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"{$src, %ax|AX, $src}">;
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"{$src, %ax|ax, $src}">;
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def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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"{$src, %eax|eax, $src}">;
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def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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"{$src, %rax|rax, $src}">;
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}
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@ -1253,13 +1253,13 @@ let isCompare = 1 in {
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} // Defs = [EFLAGS]
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def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
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"{$src, %al|AL, $src}">;
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"{$src, %al|al, $src}">;
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def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
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"{$src, %ax|AX, $src}">;
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"{$src, %ax|ax, $src}">;
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def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
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"{$src, %eax|EAX, $src}">;
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"{$src, %eax|eax, $src}">;
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def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
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"{$src, %rax|RAX, $src}">;
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"{$src, %rax|rax, $src}">;
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} // isCompare
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//===----------------------------------------------------------------------===//
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@ -229,22 +229,22 @@ class FPrST0PInst<bits<8> o, string asm>
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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// we have to put some 'r's in and take them out of weird places.
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def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
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def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, ST(0)}">;
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def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, st(0)}">;
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def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
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def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
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def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, ST(0)}">;
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def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
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def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
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def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
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def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, ST(0)}">;
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def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
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def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
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def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
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def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, ST(0)}">;
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def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, st(0)}">;
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def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
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def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
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def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, ST(0)}">;
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def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
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def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
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def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
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def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, ST(0)}">;
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def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
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def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
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def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
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@ -337,21 +337,21 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
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let Predicates = [HasCMov] in {
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// These are not factored because there's no clean way to pass DA/DB.
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def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovb\t{$op, %st(0)|ST(0), $op}">, DA;
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"fcmovb\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovbe\t{$op, %st(0)|ST(0), $op}">, DA;
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"fcmovbe\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmove\t{$op, %st(0)|ST(0), $op}">, DA;
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"fcmove\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovu\t{$op, %st(0)|ST(0), $op}">, DA;
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"fcmovu\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnb\t{$op, %st(0)|ST(0), $op}">, DB;
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"fcmovnb\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnbe\t{$op, %st(0)|ST(0), $op}">, DB;
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"fcmovnbe\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovne\t{$op, %st(0)|ST(0), $op}">, DB;
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"fcmovne\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnu\t{$op, %st(0)|ST(0), $op}">, DB;
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"fcmovnu\t{$op, %st(0)|st(0), $op}">, DB;
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} // Predicates = [HasCMov]
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// Floating point loads & stores.
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@ -578,7 +578,7 @@ def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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let SchedRW = [WriteALU] in {
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let Defs = [AX], Uses = [FPSW] in
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def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags
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(outs), (ins), "fnstsw\t{%ax|AX}",
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(outs), (ins), "fnstsw\t{%ax|ax}",
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[(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>, DF;
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def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
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@ -1076,51 +1076,51 @@ def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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/// 32-bit offset from the PC. These are only valid in x86-32 mode.
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let SchedRW = [WriteALU] in {
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def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
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"mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
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"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
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"mov{w}\t{$src, %ax|AX, $src}", [], IIC_MOV_MEM>, OpSize,
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"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
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Requires<[In32BitMode]>;
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def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
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"mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
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"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
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"mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
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"mov{w}\t{%ax, $dst|$dst, AX}", [], IIC_MOV_MEM>, OpSize,
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
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Requires<[In32BitMode]>;
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def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
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"mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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Requires<[In32BitMode]>;
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}
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// These forms all have full 64-bit absolute addresses in their instructions
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// and use the movabs mnemonic to indicate this specific form.
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def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset64:$src),
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"movabs{b}\t{$src, %al|AL, $src}", []>,
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"movabs{b}\t{$src, %al|al, $src}", []>,
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Requires<[In64BitMode]>;
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def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
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"movabs{w}\t{$src, %ax|AX, $src}", []>, OpSize,
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"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
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Requires<[In64BitMode]>;
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def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
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"movabs{l}\t{$src, %eax|AEX, $src}", []>,
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"movabs{l}\t{$src, %eax|eax, $src}", []>,
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Requires<[In64BitMode]>;
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def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
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"movabs{q}\t{$src, %rax|RAX, $src}", []>,
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"movabs{q}\t{$src, %rax|rax, $src}", []>,
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Requires<[In64BitMode]>;
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def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset64:$dst), (ins),
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"movabs{b}\t{%al, $dst|$dst, AL}", []>,
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"movabs{b}\t{%al, $dst|$dst, al}", []>,
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Requires<[In64BitMode]>;
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def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"movabs{w}\t{%ax, $dst|$dst, AX}", []>, OpSize,
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"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
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Requires<[In64BitMode]>;
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def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"movabs{l}\t{%eax, $dst|$dst, EAX}", []>,
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"movabs{l}\t{%eax, $dst|$dst, eax}", []>,
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Requires<[In64BitMode]>;
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def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"movabs{q}\t{%rax, $dst|$dst, RAX}", []>,
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"movabs{q}\t{%rax, $dst|$dst, rax}", []>,
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Requires<[In64BitMode]>;
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let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
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@ -1454,17 +1454,17 @@ def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
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// Swap between EAX and other registers.
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def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
|
||||
"xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
|
||||
"xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
|
||||
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
|
||||
"xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
|
||||
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
|
||||
Requires<[In32BitMode]>;
|
||||
// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
|
||||
// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
|
||||
def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
|
||||
"xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
|
||||
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
|
||||
Requires<[In64BitMode]>;
|
||||
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
|
||||
"xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
|
||||
"xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
|
||||
} // SchedRW
|
||||
|
||||
let SchedRW = [WriteALU] in {
|
||||
|
|
@ -2033,22 +2033,22 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
|
|||
def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
|
||||
|
||||
// div and idiv aliases for explicit A register.
|
||||
def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8r GR8 :$src)>;
|
||||
def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16r GR16:$src)>;
|
||||
def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32r GR32:$src)>;
|
||||
def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64r GR64:$src)>;
|
||||
def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8m i8mem :$src)>;
|
||||
def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16m i16mem:$src)>;
|
||||
def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32m i32mem:$src)>;
|
||||
def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64m i64mem:$src)>;
|
||||
def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8r GR8 :$src)>;
|
||||
def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16r GR16:$src)>;
|
||||
def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32r GR32:$src)>;
|
||||
def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64r GR64:$src)>;
|
||||
def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8m i8mem :$src)>;
|
||||
def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16m i16mem:$src)>;
|
||||
def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32m i32mem:$src)>;
|
||||
def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64m i64mem:$src)>;
|
||||
def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
|
||||
def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
|
||||
def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
|
||||
def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
|
||||
def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
|
||||
def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
|
||||
def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
|
||||
def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
|
||||
def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
|
||||
def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
|
||||
def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
|
||||
def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
|
||||
def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
|
||||
def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
|
||||
def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
|
||||
def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
|
||||
|
||||
|
||||
|
||||
|
|
@ -2075,9 +2075,9 @@ def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
|
|||
// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
|
||||
// gas.
|
||||
multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|ST(0), $op}"),
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
|
||||
(Inst RST:$op), EmitAlias>;
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|ST(0), ST(0)}"),
|
||||
def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
|
||||
(Inst ST0), EmitAlias>;
|
||||
}
|
||||
|
||||
|
|
@ -2102,16 +2102,16 @@ defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
|
|||
// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
|
||||
// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
|
||||
// solely because gas supports it.
|
||||
def : InstAlias<"faddp\t{%st(0), $op|$op, ST(0)}", (ADD_FPrST0 RST:$op), 0>;
|
||||
def : InstAlias<"fmulp\t{%st(0), $op|$op, ST(0)}", (MUL_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, ST(0)}", (SUBR_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, ST(0)}", (SUB_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, ST(0)}", (DIVR_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, ST(0)}", (DIV_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
|
||||
def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
|
||||
def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
|
||||
|
||||
// We accept "fnstsw %eax" even though it only writes %ax.
|
||||
def : InstAlias<"fnstsw\t{%eax|EAX}", (FNSTSW16r)>;
|
||||
def : InstAlias<"fnstsw\t{%al|AL}" , (FNSTSW16r)>;
|
||||
def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
|
||||
def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
|
||||
def : InstAlias<"fnstsw" , (FNSTSW16r)>;
|
||||
|
||||
// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
|
||||
|
|
@ -2130,9 +2130,9 @@ def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
|
|||
def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
|
||||
|
||||
// inb %dx -> inb %al, %dx
|
||||
def : InstAlias<"inb\t{%dx|DX}", (IN8rr), 0>;
|
||||
def : InstAlias<"inw\t{%dx|DX}", (IN16rr), 0>;
|
||||
def : InstAlias<"inl\t{%dx|DX}", (IN32rr), 0>;
|
||||
def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
|
||||
def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
|
||||
def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
|
||||
def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
|
||||
def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
|
||||
def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
|
||||
|
|
@ -2184,9 +2184,9 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
|
|||
// Note: No GR32->GR64 movzx form.
|
||||
|
||||
// outb %dx -> outb %al, %dx
|
||||
def : InstAlias<"outb\t{%dx|DX}", (OUT8rr), 0>;
|
||||
def : InstAlias<"outw\t{%dx|DX}", (OUT16rr), 0>;
|
||||
def : InstAlias<"outl\t{%dx|DX}", (OUT32rr), 0>;
|
||||
def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
|
||||
def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
|
||||
def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
|
||||
def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
|
||||
def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
|
||||
def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
|
||||
|
|
@ -2252,7 +2252,7 @@ def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:
|
|||
def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
|
||||
|
||||
// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
|
||||
def : InstAlias<"xchg{w}\t{%ax, $src|$src, AX}", (XCHG16ar GR16:$src)>;
|
||||
def : InstAlias<"xchg{l}\t{%eax, $src|$src, EAX}", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
|
||||
def : InstAlias<"xchg{l}\t{%eax, $src|$src, EAX}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
|
||||
def : InstAlias<"xchg{q}\t{%rax, $src|$src, RAX}", (XCHG64ar GR64:$src)>;
|
||||
def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
|
||||
def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
|
||||
def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
|
||||
def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;
|
||||
|
|
|
|||
|
|
@ -5477,12 +5477,12 @@ def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
|
|||
TB, Requires<[HasSSE3]>;
|
||||
} // SchedRW
|
||||
|
||||
def : InstAlias<"mwait\t{%eax, %ecx|ECX, EAX}", (MWAITrr)>, Requires<[In32BitMode]>;
|
||||
def : InstAlias<"mwait\t{%rax, %rcx|RCX, RAX}", (MWAITrr)>, Requires<[In64BitMode]>;
|
||||
def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
|
||||
def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
|
||||
|
||||
def : InstAlias<"monitor\t{%eax, %ecx, %edx|EDX, ECX, EAX}", (MONITORrrr)>,
|
||||
def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
|
||||
Requires<[In32BitMode]>;
|
||||
def : InstAlias<"monitor\t{%rax, %rcx, %rdx|RDX, RCX, RAX}", (MONITORrrr)>,
|
||||
def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -7016,17 +7016,17 @@ defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
|
|||
int_x86_sse41_pblendvb>;
|
||||
|
||||
// Aliases with the implicit xmm0 argument
|
||||
def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
|
||||
def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
|
||||
(BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
|
||||
def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
|
||||
def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
|
||||
(BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
|
||||
def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
|
||||
def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
|
||||
(BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
|
||||
def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
|
||||
def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
|
||||
(BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
|
||||
def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
|
||||
def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
|
||||
(PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
|
||||
def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
|
||||
def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
|
||||
(PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
|
||||
|
||||
let Predicates = [UseSSE41] in {
|
||||
|
|
|
|||
|
|
@ -26,37 +26,37 @@ def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
|
|||
|
||||
// 0F 01 DE
|
||||
let Uses = [EAX] in
|
||||
def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|EAX}", []>, TB;
|
||||
def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
|
||||
|
||||
// 0F 01 D8
|
||||
let Uses = [EAX] in
|
||||
def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
|
||||
"vmrun\t{%eax|EAX}", []>, TB, Requires<[In32BitMode]>;
|
||||
"vmrun\t{%eax|eax}", []>, TB, Requires<[In32BitMode]>;
|
||||
let Uses = [RAX] in
|
||||
def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
|
||||
"vmrun\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
|
||||
"vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
|
||||
|
||||
// 0F 01 DA
|
||||
let Uses = [EAX] in
|
||||
def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
|
||||
"vmload\t{%eax|EAX}", []>, TB, Requires<[In32BitMode]>;
|
||||
"vmload\t{%eax|eax}", []>, TB, Requires<[In32BitMode]>;
|
||||
let Uses = [RAX] in
|
||||
def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
|
||||
"vmload\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
|
||||
"vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
|
||||
|
||||
// 0F 01 DB
|
||||
let Uses = [EAX] in
|
||||
def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
|
||||
"vmsave\t{%eax|EAX}", []>, TB, Requires<[In32BitMode]>;
|
||||
"vmsave\t{%eax|eax}", []>, TB, Requires<[In32BitMode]>;
|
||||
let Uses = [RAX] in
|
||||
def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins),
|
||||
"vmsave\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
|
||||
"vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
|
||||
|
||||
// 0F 01 DF
|
||||
let Uses = [EAX, ECX] in
|
||||
def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins),
|
||||
"invlpga\t{%ecx, %eax|EAX, ECX}", []>, TB, Requires<[In32BitMode]>;
|
||||
"invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[In32BitMode]>;
|
||||
let Uses = [RAX, ECX] in
|
||||
def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins),
|
||||
"invlpga\t{%ecx, %rax|RAX, ECX}", []>, TB, Requires<[In64BitMode]>;
|
||||
"invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,16 +18,16 @@ let Defs = [EFLAGS] in {
|
|||
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
|
||||
let Uses = [CL] in {
|
||||
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"shl{b}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
|
||||
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"shl{w}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"shl{l}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
|
||||
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"shl{q}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
|
||||
} // Uses = [CL]
|
||||
|
||||
|
|
@ -70,17 +70,17 @@ let SchedRW = [WriteShiftLd, WriteRMW] in {
|
|||
// using CL?
|
||||
let Uses = [CL] in {
|
||||
def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
|
||||
"shl{b}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
|
||||
"shl{w}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
|
||||
OpSize;
|
||||
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
|
||||
"shl{l}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
|
||||
"shl{q}\t{%cl, $dst|$dst, CL}",
|
||||
"shl{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
}
|
||||
def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||
|
|
@ -124,16 +124,16 @@ def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
|
|||
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
|
||||
let Uses = [CL] in {
|
||||
def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"shr{b}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
|
||||
def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"shr{w}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"shr{l}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
|
||||
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"shr{q}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
|
||||
}
|
||||
|
||||
|
|
@ -171,17 +171,17 @@ def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
|||
let SchedRW = [WriteShiftLd, WriteRMW] in {
|
||||
let Uses = [CL] in {
|
||||
def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
|
||||
"shr{b}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
|
||||
"shr{w}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
|
||||
OpSize;
|
||||
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
|
||||
"shr{l}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
|
||||
"shr{q}\t{%cl, $dst|$dst, CL}",
|
||||
"shr{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
}
|
||||
def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||
|
|
@ -224,19 +224,19 @@ def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
|
|||
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
|
||||
let Uses = [CL] in {
|
||||
def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"sar{b}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR8:$dst, (sra GR8:$src1, CL))],
|
||||
IIC_SR>;
|
||||
def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"sar{w}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (sra GR16:$src1, CL))],
|
||||
IIC_SR>, OpSize;
|
||||
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"sar{l}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (sra GR32:$src1, CL))],
|
||||
IIC_SR>;
|
||||
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"sar{q}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (sra GR64:$src1, CL))],
|
||||
IIC_SR>;
|
||||
}
|
||||
|
|
@ -283,19 +283,19 @@ def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
|||
let SchedRW = [WriteShiftLd, WriteRMW] in {
|
||||
let Uses = [CL] in {
|
||||
def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
|
||||
"sar{b}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
|
||||
"sar{w}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize;
|
||||
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
|
||||
"sar{l}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
|
||||
"sar{q}\t{%cl, $dst|$dst, CL}",
|
||||
"sar{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
}
|
||||
|
|
@ -349,7 +349,7 @@ def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
|||
"rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
let Uses = [CL] in
|
||||
def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
"rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcl{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
|
|
@ -357,7 +357,7 @@ def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
|||
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
|
||||
let Uses = [CL] in
|
||||
def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
|
||||
def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcl{l}\t$dst", [], IIC_SR>;
|
||||
|
|
@ -365,7 +365,7 @@ def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
|||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
let Uses = [CL] in
|
||||
def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
|
||||
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
|
|
@ -374,7 +374,7 @@ def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
|
|||
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
let Uses = [CL] in
|
||||
def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
|
||||
def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
|
|
@ -383,7 +383,7 @@ def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
|||
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
let Uses = [CL] in
|
||||
def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
"rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcr{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
|
|
@ -391,7 +391,7 @@ def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
|||
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
|
||||
let Uses = [CL] in
|
||||
def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
|
||||
def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcr{l}\t$dst", [], IIC_SR>;
|
||||
|
|
@ -399,7 +399,7 @@ def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
|||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
let Uses = [CL] in
|
||||
def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rcr{q}\t$dst", [], IIC_SR>;
|
||||
|
|
@ -407,7 +407,7 @@ def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
|
|||
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
let Uses = [CL] in
|
||||
def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
} // Constraints = "$src = $dst"
|
||||
|
||||
|
|
@ -448,22 +448,22 @@ def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
|
|||
|
||||
let Uses = [CL] in {
|
||||
def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
|
||||
"rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
|
||||
"rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
|
||||
"rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
|
||||
"rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
|
||||
"rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
|
||||
"rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
|
||||
"rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
}
|
||||
} // SchedRW
|
||||
} // hasSideEffects = 0
|
||||
|
|
@ -472,16 +472,16 @@ let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
|
|||
// FIXME: provide shorter instructions when imm8 == 1
|
||||
let Uses = [CL] in {
|
||||
def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"rol{b}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
|
||||
def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rol{w}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rol{l}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
|
||||
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rol{q}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
|
||||
}
|
||||
|
||||
|
|
@ -525,19 +525,19 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
|||
let SchedRW = [WriteShiftLd, WriteRMW] in {
|
||||
let Uses = [CL] in {
|
||||
def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
|
||||
"rol{b}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
|
||||
"rol{w}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize;
|
||||
def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
|
||||
"rol{l}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
|
||||
"rol{q}\t{%cl, $dst|$dst, CL}",
|
||||
"rol{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
}
|
||||
|
|
@ -582,16 +582,16 @@ def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
|
|||
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
|
||||
let Uses = [CL] in {
|
||||
def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
"ror{b}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
|
||||
def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"ror{w}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"ror{l}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
|
||||
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"ror{q}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
|
||||
}
|
||||
|
||||
|
|
@ -635,19 +635,19 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
|||
let SchedRW = [WriteShiftLd, WriteRMW] in {
|
||||
let Uses = [CL] in {
|
||||
def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
|
||||
"ror{b}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{b}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
|
||||
"ror{w}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize;
|
||||
def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
|
||||
"ror{l}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
|
||||
"ror{q}\t{%cl, $dst|$dst, CL}",
|
||||
"ror{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>;
|
||||
}
|
||||
|
|
@ -699,35 +699,35 @@ let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
|
|||
let Uses = [CL] in {
|
||||
def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
|
||||
(ins GR16:$src1, GR16:$src2),
|
||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
|
||||
IIC_SHD16_REG_CL>,
|
||||
TB, OpSize;
|
||||
def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
|
||||
(ins GR16:$src1, GR16:$src2),
|
||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
|
||||
IIC_SHD16_REG_CL>,
|
||||
TB, OpSize;
|
||||
def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2),
|
||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
|
||||
IIC_SHD32_REG_CL>, TB;
|
||||
def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2),
|
||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
|
||||
IIC_SHD32_REG_CL>, TB;
|
||||
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
|
||||
(ins GR64:$src1, GR64:$src2),
|
||||
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
|
||||
IIC_SHD64_REG_CL>,
|
||||
TB;
|
||||
def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
|
||||
(ins GR64:$src1, GR64:$src2),
|
||||
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
|
||||
IIC_SHD64_REG_CL>,
|
||||
TB;
|
||||
|
|
@ -782,29 +782,29 @@ def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
|
|||
let SchedRW = [WriteShiftLd, WriteRMW] in {
|
||||
let Uses = [CL] in {
|
||||
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
|
||||
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
|
||||
def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
|
||||
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
|
||||
|
||||
def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
|
||||
addr:$dst)], IIC_SHD32_MEM_CL>, TB;
|
||||
def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
|
||||
addr:$dst)], IIC_SHD32_MEM_CL>, TB;
|
||||
|
||||
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
|
||||
addr:$dst)], IIC_SHD64_MEM_CL>, TB;
|
||||
def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
||||
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
|
||||
addr:$dst)], IIC_SHD64_MEM_CL>, TB;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -77,43 +77,43 @@ def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
|
|||
let SchedRW = [WriteSystem] in {
|
||||
let Defs = [AL], Uses = [DX] in
|
||||
def IN8rr : I<0xEC, RawFrm, (outs), (ins),
|
||||
"in{b}\t{%dx, %al|AL, DX}", [], IIC_IN_RR>;
|
||||
"in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
|
||||
let Defs = [AX], Uses = [DX] in
|
||||
def IN16rr : I<0xED, RawFrm, (outs), (ins),
|
||||
"in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize;
|
||||
"in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
|
||||
let Defs = [EAX], Uses = [DX] in
|
||||
def IN32rr : I<0xED, RawFrm, (outs), (ins),
|
||||
"in{l}\t{%dx, %eax|EAX, DX}", [], IIC_IN_RR>;
|
||||
"in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>;
|
||||
|
||||
let Defs = [AL] in
|
||||
def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
|
||||
"in{b}\t{$port, %al|AL, $port}", [], IIC_IN_RI>;
|
||||
"in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
|
||||
let Defs = [AX] in
|
||||
def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
|
||||
"in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize;
|
||||
"in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
|
||||
let Defs = [EAX] in
|
||||
def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
|
||||
"in{l}\t{$port, %eax|EAX, $port}", [], IIC_IN_RI>;
|
||||
"in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>;
|
||||
|
||||
let Uses = [DX, AL] in
|
||||
def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
|
||||
"out{b}\t{%al, %dx|DX, AL}", [], IIC_OUT_RR>;
|
||||
"out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
|
||||
let Uses = [DX, AX] in
|
||||
def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
|
||||
"out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize;
|
||||
"out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
|
||||
let Uses = [DX, EAX] in
|
||||
def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
|
||||
"out{l}\t{%eax, %dx|DX, EAX}", [], IIC_OUT_RR>;
|
||||
"out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>;
|
||||
|
||||
let Uses = [AL] in
|
||||
def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
|
||||
"out{b}\t{%al, $port|$port, AL}", [], IIC_OUT_IR>;
|
||||
"out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
|
||||
let Uses = [AX] in
|
||||
def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||
"out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize;
|
||||
"out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
|
||||
let Uses = [EAX] in
|
||||
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||
"out{l}\t{%eax, $port|$port, EAX}", [], IIC_OUT_IR>;
|
||||
"out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>;
|
||||
|
||||
def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
|
||||
def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
|
||||
|
|
@ -248,75 +248,75 @@ def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
|
|||
"ltr{w}\t$src", [], IIC_LTR>, TB;
|
||||
|
||||
def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%cs|CS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
"push{w}\t{%cs|cs}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%cs|CS}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%cs|cs}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
|
||||
def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
"push{w}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
"push{w}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
"push{w}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
|
||||
def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%fs|FS}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
"push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%fs|FS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
|
||||
def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%gs|GS}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
"push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%gs|GS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
|
||||
|
||||
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{q}\t{%fs|FS}", [], IIC_PUSH_SR>, TB;
|
||||
"push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB;
|
||||
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{q}\t{%gs|GS}", [], IIC_PUSH_SR>, TB;
|
||||
"push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB;
|
||||
|
||||
// No "pop cs" instruction.
|
||||
def POPSS16 : I<0x17, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%ss|SS}", [], IIC_POP_SR_SS>,
|
||||
"pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
|
||||
OpSize, Requires<[In32BitMode]>;
|
||||
def POPSS32 : I<0x17, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%ss|SS}", [], IIC_POP_SR_SS>,
|
||||
"pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%ds|DS}", [], IIC_POP_SR>,
|
||||
"pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
|
||||
OpSize, Requires<[In32BitMode]>;
|
||||
def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%ds|DS}", [], IIC_POP_SR>,
|
||||
"pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def POPES16 : I<0x07, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%es|ES}", [], IIC_POP_SR>,
|
||||
"pop{w}\t{%es|es}", [], IIC_POP_SR>,
|
||||
OpSize, Requires<[In32BitMode]>;
|
||||
def POPES32 : I<0x07, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%es|ES}", [], IIC_POP_SR>,
|
||||
"pop{l}\t{%es|es}", [], IIC_POP_SR>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%fs|FS}", [], IIC_POP_SR>, OpSize, TB;
|
||||
"pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
|
||||
def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%fs|FS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
|
||||
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{q}\t{%fs|FS}", [], IIC_POP_SR>, TB;
|
||||
"pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB;
|
||||
|
||||
def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%gs|GS}", [], IIC_POP_SR>, OpSize, TB;
|
||||
"pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
|
||||
def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%gs|GS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
|
||||
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{q}\t{%gs|GS}", [], IIC_POP_SR>, TB;
|
||||
"pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB;
|
||||
|
||||
|
||||
def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc < %s -mcpu=generic -march=x86 -x86-asm-syntax=intel | FileCheck %s
|
||||
; CHECK: add ESP, 8
|
||||
; CHECK: add esp, 8
|
||||
|
||||
target triple = "i686-pc-linux-gnu"
|
||||
|
||||
|
|
|
|||
|
|
@ -5,25 +5,25 @@ declare x86_fastcallcc i64 @callee(i64 inreg)
|
|||
|
||||
define i64 @caller() {
|
||||
%X = call x86_fastcallcc i64 @callee( i64 4294967299 ) ; <i64> [#uses=1]
|
||||
; CHECK: mov{{.*}}EDX, 1
|
||||
; CHECK: mov{{.*}}edx, 1
|
||||
ret i64 %X
|
||||
}
|
||||
|
||||
define x86_fastcallcc i64 @caller2(i64 inreg %X) {
|
||||
ret i64 %X
|
||||
; CHECK: mov{{.*}}EAX, ECX
|
||||
; CHECK: mov{{.*}}eax, ecx
|
||||
}
|
||||
|
||||
declare x86_thiscallcc i64 @callee2(i32)
|
||||
|
||||
define i64 @caller3() {
|
||||
%X = call x86_thiscallcc i64 @callee2( i32 3 )
|
||||
; CHECK: mov{{.*}}ECX, 3
|
||||
; CHECK: mov{{.*}}ecx, 3
|
||||
ret i64 %X
|
||||
}
|
||||
|
||||
define x86_thiscallcc i32 @caller4(i32 %X) {
|
||||
ret i32 %X
|
||||
; CHECK: mov{{.*}}EAX, ECX
|
||||
; CHECK: mov{{.*}}eax, ecx
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -7,40 +7,40 @@ define double @foo_add(double %P) {
|
|||
ret double %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: foo_add:
|
||||
; CHECK: fadd DWORD PTR
|
||||
; CHECK: fadd dword ptr
|
||||
|
||||
define double @foo_mul(double %P) {
|
||||
%tmp.1 = fmul double %P, 1.230000e+02 ; <double> [#uses=1]
|
||||
ret double %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: foo_mul:
|
||||
; CHECK: fmul DWORD PTR
|
||||
; CHECK: fmul dword ptr
|
||||
|
||||
define double @foo_sub(double %P) {
|
||||
%tmp.1 = fsub double %P, 1.230000e+02 ; <double> [#uses=1]
|
||||
ret double %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: foo_sub:
|
||||
; CHECK: fadd DWORD PTR
|
||||
; CHECK: fadd dword ptr
|
||||
|
||||
define double @foo_subr(double %P) {
|
||||
%tmp.1 = fsub double 1.230000e+02, %P ; <double> [#uses=1]
|
||||
ret double %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: foo_subr:
|
||||
; CHECK: fsub QWORD PTR
|
||||
; CHECK: fsub qword ptr
|
||||
|
||||
define double @foo_div(double %P) {
|
||||
%tmp.1 = fdiv double %P, 1.230000e+02 ; <double> [#uses=1]
|
||||
ret double %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: foo_div:
|
||||
; CHECK: fdiv DWORD PTR
|
||||
; CHECK: fdiv dword ptr
|
||||
|
||||
define double @foo_divr(double %P) {
|
||||
%tmp.1 = fdiv double 1.230000e+02, %P ; <double> [#uses=1]
|
||||
ret double %tmp.1
|
||||
}
|
||||
; CHECK-LABEL: foo_divr:
|
||||
; CHECK: fdiv QWORD PTR
|
||||
; CHECK: fdiv qword ptr
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ define i32 @test1(i32 %A, i32 %B) {
|
|||
; The above computation of %tmp4 should match a single lea, without using
|
||||
; actual add instructions.
|
||||
; CHECK-NOT: add
|
||||
; CHECK: lea {{[A-Z]+}}, DWORD PTR [{{[A-Z]+}} + 4*{{[A-Z]+}} - 5]
|
||||
; CHECK: lea {{[a-z]+}}, dword ptr [{{[a-z]+}} + 4*{{[a-z]+}} - 5]
|
||||
|
||||
ret i32 %tmp4
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
|
||||
; RUN: grep "shld.*CL"
|
||||
; RUN: grep "shld.*cl"
|
||||
; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
|
||||
; RUN: not grep "mov CL, BL"
|
||||
; RUN: not grep "mov cl, bl"
|
||||
|
||||
; PR687
|
||||
|
||||
|
|
|
|||
|
|
@ -17,10 +17,10 @@ cond_true2732.preheader: ; preds = %entry
|
|||
store i64 %tmp2676.us.us, i64* %tmp2666
|
||||
ret i32 0
|
||||
|
||||
; INTEL: and {{E..}}, DWORD PTR [360]
|
||||
; INTEL: and DWORD PTR [356], {{E..}}
|
||||
; FIXME: mov DWORD PTR [360], {{E..}}
|
||||
; The above line comes out as 'mov 360, EAX', but when the register is ECX it works?
|
||||
; INTEL: and {{e..}}, dword ptr [360]
|
||||
; INTEL: and dword ptr [356], {{e..}}
|
||||
; FIXME: mov dword ptr [360], {{e..}}
|
||||
; The above line comes out as 'mov 360, eax', but when the register is ecx it works?
|
||||
|
||||
; ATT: andl 360, %{{e..}}
|
||||
; ATT: andl %{{e..}}, 356
|
||||
|
|
|
|||
|
|
@ -12,70 +12,70 @@
|
|||
# CHECK: movsq
|
||||
0x48 0xa5
|
||||
|
||||
# CHECK: pop FS
|
||||
# CHECK: pop fs
|
||||
0x0f 0xa1
|
||||
|
||||
# CHECK: pop GS
|
||||
# CHECK: pop gs
|
||||
0x0f 0xa9
|
||||
|
||||
# CHECK: in AL, DX
|
||||
# CHECK: in al, dx
|
||||
0xec
|
||||
|
||||
# CHECK: nop
|
||||
0x90
|
||||
|
||||
# CHECK: xchg EAX, R8D
|
||||
# CHECK: xchg eax, r8d
|
||||
0x41 0x90
|
||||
|
||||
# CHECK: xchg RAX, R8
|
||||
# CHECK: xchg rax, r8
|
||||
0x49 0x90
|
||||
|
||||
# CHECK: add AL, 0
|
||||
# CHECK: add al, 0
|
||||
0x04 0x00
|
||||
|
||||
# CHECK: add AX, 0
|
||||
# CHECK: add ax, 0
|
||||
0x66 0x05 0x00 0x00
|
||||
|
||||
# CHECK: add EAX, 0
|
||||
# CHECK: add eax, 0
|
||||
0x05 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: add RAX, 0
|
||||
# CHECK: add rax, 0
|
||||
0x48 0x05 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: adc AL, 0
|
||||
# CHECK: adc al, 0
|
||||
0x14 0x00
|
||||
|
||||
# CHECK: adc AX, 0
|
||||
# CHECK: adc ax, 0
|
||||
0x66 0x15 0x00 0x00
|
||||
|
||||
# CHECK: adc EAX, 0
|
||||
# CHECK: adc eax, 0
|
||||
0x15 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: adc RAX, 0
|
||||
# CHECK: adc rax, 0
|
||||
0x48 0x15 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: cmp AL, 0
|
||||
# CHECK: cmp al, 0
|
||||
0x3c 0x00
|
||||
|
||||
# CHECK: cmp AX, 0
|
||||
# CHECK: cmp ax, 0
|
||||
0x66 0x3d 0x00 0x00
|
||||
|
||||
# CHECK: cmp EAX, 0
|
||||
# CHECK: cmp eax, 0
|
||||
0x3d 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: cmp RAX, 0
|
||||
# CHECK: cmp rax, 0
|
||||
0x48 0x3d 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: test AL, 0
|
||||
# CHECK: test al, 0
|
||||
0xa8 0x00
|
||||
|
||||
# CHECK: test AX, 0
|
||||
# CHECK: test ax, 0
|
||||
0x66 0xa9 0x00 0x00
|
||||
|
||||
# CHECK: test EAX, 0
|
||||
# CHECK: test eax, 0
|
||||
0xa9 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: test RAX, 0
|
||||
# CHECK: test rax, 0
|
||||
0x48 0xa9 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: sysret
|
||||
|
|
@ -105,17 +105,17 @@
|
|||
# CHECK: retf
|
||||
0x66 0xcb
|
||||
|
||||
# CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0
|
||||
# CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0
|
||||
0xc4 0xe2 0xfd 0x91 0x14 0x4f
|
||||
|
||||
# CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
|
||||
# CHECK: vpgatherdd xmm10, dword ptr [r15 + 2*xmm9], xmm8
|
||||
0xc4 0x02 0x39 0x90 0x14 0x4f
|
||||
|
||||
# CHECK: xsave64 OPAQUE PTR [RAX]
|
||||
# CHECK: xsave64 opaque ptr [rax]
|
||||
0x48 0x0f 0xae 0x20
|
||||
|
||||
# CHECK: xrstor64 OPAQUE PTR [RAX]
|
||||
# CHECK: xrstor64 opaque ptr [rax]
|
||||
0x48 0x0f 0xae 0x28
|
||||
|
||||
# CHECK: xsaveopt64 OPAQUE PTR [RAX]
|
||||
# CHECK: xsaveopt64 opaque ptr [rax]
|
||||
0x48 0x0f 0xae 0x30
|
||||
|
|
|
|||
Loading…
Reference in New Issue