forked from OSchip/llvm-project
[Hexagon] Partially revert r309230 which caused some build bots failures.
llvm-svn: 309233
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4b075bb218
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@ -1,4 +1,4 @@
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//===- HexagonBlockRanges.h -------------------------------------*- C++ -*-===//
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//===--- HexagonBlockRanges.h -----------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -10,6 +10,7 @@
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#define HEXAGON_BLOCK_RANGES_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include <cassert>
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#include <map>
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#include <set>
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@ -22,7 +23,6 @@ class HexagonSubtarget;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class raw_ostream;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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@ -32,12 +32,11 @@ struct HexagonBlockRanges {
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struct RegisterRef {
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unsigned Reg, Sub;
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bool operator<(RegisterRef R) const {
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return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
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}
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};
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using RegisterSet = std::set<RegisterRef>;
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typedef std::set<RegisterRef> RegisterSet;
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// This is to represent an "index", which is an abstraction of a position
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// of an instruction within a basic block.
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@ -50,7 +49,7 @@ struct HexagonBlockRanges {
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First = 11 // 10th + 1st
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};
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IndexType() = default;
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IndexType() : Index(None) {}
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IndexType(unsigned Idx) : Index(Idx) {}
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static bool isInstr(IndexType X) { return X.Index >= First; }
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@ -69,13 +68,13 @@ struct HexagonBlockRanges {
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bool operator> (IndexType Idx) const;
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bool operator>= (IndexType Idx) const;
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unsigned Index = None;
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unsigned Index;
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};
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// A range of indices, essentially a representation of a live range.
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// This is also used to represent "dead ranges", i.e. ranges where a
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// register is dead.
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class IndexRange : public std::pair<IndexType, IndexType> {
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class IndexRange : public std::pair<IndexType,IndexType> {
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public:
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IndexRange() = default;
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IndexRange(IndexType Start, IndexType End, bool F = false, bool T = false)
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@ -139,8 +138,7 @@ struct HexagonBlockRanges {
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std::map<IndexType,MachineInstr*> Map;
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};
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using RegToRangeMap = std::map<RegisterRef, RangeList>;
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typedef std::map<RegisterRef,RangeList> RegToRangeMap;
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RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap);
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RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap);
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static RegisterSet expandToSubRegs(RegisterRef R,
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