forked from OSchip/llvm-project
[AArch64] add tests for vector load combining; NFC
More coverage for D133584
This commit is contained in:
Sanjay Patel
parent
e56b507447
commit
ef7d61d67c
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@ -561,3 +561,199 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
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%tmp8 = or i32 %tmp7, %tmp30
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ret i32 %tmp8
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}
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define void @short_vector_to_i32(<4 x i8>* %in, i32* %out, i32* %p) {
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; CHECK-LABEL: short_vector_to_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: umov w8, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[1]
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; CHECK-NEXT: umov w10, v0.h[2]
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; CHECK-NEXT: umov w11, v0.h[3]
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; CHECK-NEXT: bfi w8, w9, #8, #8
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; CHECK-NEXT: bfi w8, w10, #16, #8
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; CHECK-NEXT: bfi w8, w11, #24, #8
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i8>, <4 x i8>* %in, align 4
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%e1 = extractelement <4 x i8> %ld, i32 0
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%e2 = extractelement <4 x i8> %ld, i32 1
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%e3 = extractelement <4 x i8> %ld, i32 2
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%e4 = extractelement <4 x i8> %ld, i32 3
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%z0 = zext i8 %e1 to i32
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%z1 = zext i8 %e2 to i32
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%z2 = zext i8 %e3 to i32
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%z3 = zext i8 %e4 to i32
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%s1 = shl nuw nsw i32 %z1, 8
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%s2 = shl nuw nsw i32 %z2, 16
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%s3 = shl nuw i32 %z3, 24
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%i1 = or i32 %s1, %z0
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%i2 = or i32 %i1, %s2
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%i3 = or i32 %i2, %s3
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store i32 %i3, i32* %out
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ret void
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}
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define void @short_vector_to_i32_unused_low_i8(<4 x i8>* %in, i32* %out, i32* %p) {
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; CHECK-LABEL: short_vector_to_i32_unused_low_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: umov w8, v0.h[2]
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; CHECK-NEXT: umov w9, v0.h[1]
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; CHECK-NEXT: umov w10, v0.h[3]
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; CHECK-NEXT: lsl w8, w8, #16
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; CHECK-NEXT: bfi w8, w9, #8, #8
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; CHECK-NEXT: bfi w8, w10, #24, #8
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i8>, <4 x i8>* %in, align 4
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%e2 = extractelement <4 x i8> %ld, i32 1
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%e3 = extractelement <4 x i8> %ld, i32 2
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%e4 = extractelement <4 x i8> %ld, i32 3
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%z1 = zext i8 %e2 to i32
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%z2 = zext i8 %e3 to i32
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%z3 = zext i8 %e4 to i32
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%s1 = shl nuw nsw i32 %z1, 8
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%s2 = shl nuw nsw i32 %z2, 16
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%s3 = shl nuw i32 %z3, 24
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%i2 = or i32 %s1, %s2
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%i3 = or i32 %i2, %s3
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store i32 %i3, i32* %out
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ret void
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}
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define void @short_vector_to_i32_unused_high_i8(<4 x i8>* %in, i32* %out, i32* %p) {
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; CHECK-LABEL: short_vector_to_i32_unused_high_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: umov w8, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[1]
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; CHECK-NEXT: umov w10, v0.h[2]
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; CHECK-NEXT: bfi w8, w9, #8, #8
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; CHECK-NEXT: bfi w8, w10, #16, #8
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i8>, <4 x i8>* %in, align 4
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%e1 = extractelement <4 x i8> %ld, i32 0
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%e2 = extractelement <4 x i8> %ld, i32 1
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%e3 = extractelement <4 x i8> %ld, i32 2
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%z0 = zext i8 %e1 to i32
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%z1 = zext i8 %e2 to i32
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%z2 = zext i8 %e3 to i32
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%s1 = shl nuw nsw i32 %z1, 8
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%s2 = shl nuw nsw i32 %z2, 16
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%i1 = or i32 %s1, %z0
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%i2 = or i32 %i1, %s2
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store i32 %i2, i32* %out
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ret void
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}
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define void @short_vector_to_i32_unused_low_i16(<4 x i8>* %in, i32* %out, i32* %p) {
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; CHECK-LABEL: short_vector_to_i32_unused_low_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: umov w8, v0.h[3]
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; CHECK-NEXT: umov w9, v0.h[2]
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; CHECK-NEXT: lsl w8, w8, #24
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; CHECK-NEXT: bfi w8, w9, #16, #8
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i8>, <4 x i8>* %in, align 4
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%e3 = extractelement <4 x i8> %ld, i32 2
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%e4 = extractelement <4 x i8> %ld, i32 3
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%z2 = zext i8 %e3 to i32
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%z3 = zext i8 %e4 to i32
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%s2 = shl nuw nsw i32 %z2, 16
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%s3 = shl nuw i32 %z3, 24
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%i3 = or i32 %s2, %s3
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store i32 %i3, i32* %out
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ret void
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}
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define void @short_vector_to_i32_unused_high_i16(<4 x i8>* %in, i32* %out, i32* %p) {
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; CHECK-LABEL: short_vector_to_i32_unused_high_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: umov w8, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[1]
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; CHECK-NEXT: bfi w8, w9, #8, #8
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i8>, <4 x i8>* %in, align 4
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%e1 = extractelement <4 x i8> %ld, i32 0
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%e2 = extractelement <4 x i8> %ld, i32 1
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%z0 = zext i8 %e1 to i32
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%z1 = zext i8 %e2 to i32
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%s1 = shl nuw nsw i32 %z1, 8
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%i1 = or i32 %s1, %z0
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store i32 %i1, i32* %out
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ret void
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}
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define void @short_vector_to_i64(<4 x i8>* %in, i64* %out, i64* %p) {
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; CHECK-LABEL: short_vector_to_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: umov w8, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[1]
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; CHECK-NEXT: umov w10, v0.h[2]
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; CHECK-NEXT: umov w11, v0.h[3]
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; CHECK-NEXT: bfi x8, x9, #8, #8
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; CHECK-NEXT: bfi x8, x10, #16, #8
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; CHECK-NEXT: bfi x8, x11, #24, #8
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; CHECK-NEXT: str x8, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i8>, <4 x i8>* %in, align 4
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%e1 = extractelement <4 x i8> %ld, i32 0
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%e2 = extractelement <4 x i8> %ld, i32 1
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%e3 = extractelement <4 x i8> %ld, i32 2
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%e4 = extractelement <4 x i8> %ld, i32 3
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%z0 = zext i8 %e1 to i64
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%z1 = zext i8 %e2 to i64
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%z2 = zext i8 %e3 to i64
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%z3 = zext i8 %e4 to i64
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%s1 = shl nuw nsw i64 %z1, 8
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%s2 = shl nuw nsw i64 %z2, 16
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%s3 = shl nuw i64 %z3, 24
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%i1 = or i64 %s1, %z0
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%i2 = or i64 %i1, %s2
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%i3 = or i64 %i2, %s3
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store i64 %i3, i64* %out
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ret void
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}
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