forked from OSchip/llvm-project
MIR Statepoint refactoring. Part 1: Basic MI level changes.
Basic support for variadic-def MIR Statepoint: - Change TableGen STATEPOINT description to variadic out list (For self-documentation purpose; by itself it does not affect code generation in any way). - Update StatepointOpers helper class to handle variadic defs. - Update MachineVerifier to properly handle them, too. With this change, new Statepoint instruction can be passed through backend (excluding ISEL) without errors. Full change set is available at D81603. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D81645
This commit is contained in:
Denis Antrushin
parent
d909764cc7
commit
ef658ebd62
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@ -166,21 +166,23 @@ class StatepointOpers {
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enum { CCOffset = 1, FlagsOffset = 3, NumDeoptOperandsOffset = 5 };
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public:
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explicit StatepointOpers(const MachineInstr *MI) : MI(MI) {}
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explicit StatepointOpers(const MachineInstr *MI) : MI(MI) {
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NumDefs = MI->getNumDefs();
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}
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/// Get index of statepoint ID operand.
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unsigned getIDPos() const { return IDPos; }
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unsigned getIDPos() const { return NumDefs + IDPos; }
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/// Get index of Num Patch Bytes operand.
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unsigned getNBytesPos() const { return NBytesPos; }
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unsigned getNBytesPos() const { return NumDefs + NBytesPos; }
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/// Get index of Num Call Arguments operand.
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unsigned getNCallArgsPos() const { return NCallArgsPos; }
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unsigned getNCallArgsPos() const { return NumDefs + NCallArgsPos; }
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/// Get starting index of non call related arguments
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/// (calling convention, statepoint flags, vm state and gc state).
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unsigned getVarIdx() const {
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return MI->getOperand(NCallArgsPos).getImm() + MetaEnd;
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return MI->getOperand(NumDefs + NCallArgsPos).getImm() + MetaEnd + NumDefs;
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}
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/// Get index of Calling Convention operand.
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@ -195,16 +197,16 @@ public:
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}
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/// Return the ID for the given statepoint.
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uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }
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uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); }
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/// Return the number of patchable bytes the given statepoint should emit.
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uint32_t getNumPatchBytes() const {
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return MI->getOperand(NBytesPos).getImm();
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return MI->getOperand(NumDefs + NBytesPos).getImm();
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}
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/// Return the target of the underlying call.
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const MachineOperand &getCallTarget() const {
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return MI->getOperand(CallTargetPos);
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return MI->getOperand(NumDefs + CallTargetPos);
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}
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/// Return the calling convention.
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@ -217,6 +219,7 @@ public:
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private:
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const MachineInstr *MI;
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unsigned NumDefs;
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};
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class StackMaps {
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@ -1157,7 +1157,7 @@ def PATCHPOINT : StandardPseudoInstruction {
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let usesCustomInserter = 1;
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}
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def STATEPOINT : StandardPseudoInstruction {
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let OutOperandList = (outs);
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let OutOperandList = (outs variable_ops);
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let InOperandList = (ins variable_ops);
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let usesCustomInserter = 1;
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let mayLoad = 1;
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@ -1565,6 +1565,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
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NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
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if (MCID.getOpcode() == TargetOpcode::STATEPOINT)
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NumDefs = MI->getNumDefs();
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// The first MCID.NumDefs operands must be explicit register defines
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if (MONum < NumDefs) {
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const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
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@ -0,0 +1,156 @@
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# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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# RUN: llc -o - %s -start-after=finalize-isel | FileCheck %s
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--- |
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; ModuleID = 'test/CodeGen/X86/statepoint-vreg.ll'
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source_filename = "test/CodeGen/X86/statepoint-vreg.ll"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-linux-gnu"
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declare void @bar()
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define i32 @test_basic(i32 addrspace(1)* %obj1, i32 addrspace(1)* %obj2) gc "statepoint-example" {
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; CHECK-LABEL: test_basic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset %rbx, -24
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; CHECK-NEXT: .cfi_offset %r14, -16
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; CHECK-NEXT: movq %rsi, %r14
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: callq bar
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; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: movl (%rbx), %eax
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; CHECK-NEXT: addl (%r14), %eax
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 0, i32 0, i32 0) [ "gc-live"(i32 addrspace(1)* %obj1, i32 addrspace(1)* %obj2) ]
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%rel1 = call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 0, i32 0) ; (%obj1, %obj1)
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%rel2 = call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 1, i32 1) ; (%obj2, %obj2)
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%a = load i32, i32 addrspace(1)* %rel1, align 4
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%b = load i32, i32 addrspace(1)* %rel2, align 4
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%c = add i32 %a, %b
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ret i32 %c
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}
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; CHECK-LABEL: __LLVM_StackMaps:
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 1
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .long 1
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; CHECK-NEXT: .quad test_basic
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; CHECK-NEXT: .quad 24
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad 2882400000
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; CHECK-NEXT: .long .Ltmp0-test_basic
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 1
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 14
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 14
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 3
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 3
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .p2align 3
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declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 immarg, i32 immarg, void ()*, i32 immarg, i32 immarg, ...)
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; Function Attrs: nounwind readonly
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declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32 immarg, i32 immarg) #0
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attributes #0 = { nounwind readonly }
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attributes #1 = { nounwind }
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...
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---
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name: test_basic
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alignment: 16
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: gr64, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr64, preferred-register: '' }
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- { id: 4, class: gr32, preferred-register: '' }
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- { id: 5, class: gr32, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$rsi', virtual-reg: '%1' }
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $rdi, $rsi
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%1:gr64 = COPY $rsi
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%0:gr64 = COPY $rdi
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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%2:gr64, %3:gr64 = STATEPOINT 2882400000, 0, 0, @bar, 2, 0, 2, 0, 2, 1, 2, 0, %1, %1(tied-def 0), %0, %0(tied-def 1), csr_64, implicit-def $rsp, implicit-def $ssp
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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%4:gr32 = MOV32rm killed %3, 1, $noreg, 0, $noreg :: (load 4 from %ir.rel1, addrspace 1)
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%5:gr32 = ADD32rm %4, killed %2, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.rel2, addrspace 1)
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$eax = COPY %5
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RET 0, $eax
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...
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