forked from OSchip/llvm-project
[BOLT] Added Constant and Copy Propagation to tail duplicated blocks
Summary: Added a function in TailDuplication that will do Constant and Copy Propagation for blocks that we duplicated as a part of tail duplication. Added supporting functions to MCPlusBuilder to find src registers and replace registers (cherry picked from FBD30231907)
This commit is contained in:
Joey Thaman
Maksim Panchenko
parent
2a5790b670
commit
ef6186c822
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@ -369,6 +369,42 @@ void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
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}
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}
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void MCPlusBuilder::getSrcRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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if (isCall(Inst)) {
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BitVector CallRegs = BitVector(Regs.size(), false);
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getCalleeSavedRegs(CallRegs);
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CallRegs.flip();
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Regs |= CallRegs;
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return;
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}
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if (isReturn(Inst)) {
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getDefaultLiveOut(Regs);
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return;
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}
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if (isRep(Inst)) {
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getRepRegs(Regs);
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}
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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}
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for (unsigned I = InstInfo.getNumDefs(), E = InstInfo.getNumOperands();
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I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
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}
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}
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bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
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const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
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return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
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@ -355,6 +355,12 @@ public:
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return Analysis->isConditionalBranch(Inst);
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}
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/// Returns true if Inst is a condtional move instruction
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virtual bool isConditionalMove(const MCInst &Inst) const {
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llvm_unreachable("not implemented");
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return false;
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}
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virtual bool isUnconditionalBranch(const MCInst &Inst) const {
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return Analysis->isUnconditionalBranch(Inst);
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}
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@ -469,6 +475,11 @@ public:
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return false;
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}
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virtual bool isRep(const MCInst &Inst) const {
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llvm_unreachable("not implemented");
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return false;
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}
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virtual bool deleteREPPrefix(MCInst &Inst) const {
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llvm_unreachable("not implemented");
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return false;
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@ -972,6 +983,20 @@ public:
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return false;
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}
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// Replace Register in Inst with Imm. Returns true if successful
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virtual bool replaceRegWithImm(MCInst &Inst, unsigned Register,
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int64_t Imm) const {
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llvm_unreachable("not implemented");
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return false;
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}
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// Replace ToReplace in Inst with ReplaceWith. Returns true if successful
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virtual bool replaceRegWithReg(MCInst &Inst, unsigned ToReplace,
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unsigned ReplaceWith) const {
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llvm_unreachable("not implemented");
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return false;
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}
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/// Add \p NewImm to the current immediate operand of \p Inst. If it is a
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/// memory accessing instruction, this immediate is the memory address
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/// displacement. Otherwise, the target operand is the first immediate
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@ -1139,6 +1164,11 @@ public:
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llvm_unreachable("not implemented");
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}
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/// Set of Registers used by the Rep instruction
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virtual void getRepRegs(BitVector &Regs) const {
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llvm_unreachable("not implemented");
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}
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/// Return the register width in bytes (1, 2, 4 or 8)
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virtual uint8_t getRegSize(MCPhysReg Reg) const;
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@ -1182,6 +1212,10 @@ public:
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/// but only if they are strictly smaller than the actual reg
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virtual void getUsedRegs(const MCInst &Inst, BitVector &Regs) const;
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/// Set of all src registers -- includes aliases but
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/// only if they are strictly smaller than the actual reg
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virtual void getSrcRegs(const MCInst &Inst, BitVector &Regs) const;
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/// Return true if this instruction defines the specified physical
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/// register either explicitly or implicitly.
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virtual bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const;
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@ -41,6 +41,179 @@ static cl::opt<unsigned> TailDuplicationMaximumDuplication(
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namespace llvm {
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namespace bolt {
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void TailDuplication::getCallerSavedRegs(const MCInst &Inst, BitVector &Regs,
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BinaryContext &BC) const {
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if (!BC.MIB->isCall(Inst))
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return;
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BitVector CallRegs = BitVector(BC.MRI->getNumRegs(), false);
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BC.MIB->getCalleeSavedRegs(CallRegs);
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CallRegs.flip();
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Regs |= CallRegs;
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}
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bool TailDuplication::regIsPossiblyOverwritten(const MCInst &Inst, unsigned Reg,
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BinaryContext &BC) const {
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BitVector WrittenRegs = BitVector(BC.MRI->getNumRegs(), false);
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BC.MIB->getWrittenRegs(Inst, WrittenRegs);
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getCallerSavedRegs(Inst, WrittenRegs, BC);
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if (BC.MIB->isRep(Inst))
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BC.MIB->getRepRegs(WrittenRegs);
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WrittenRegs &= BC.MIB->getAliases(Reg, false);
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return WrittenRegs.any();
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}
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bool TailDuplication::regIsDefinitelyOverwritten(const MCInst &Inst,
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unsigned Reg,
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BinaryContext &BC) const {
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BitVector WrittenRegs = BitVector(BC.MRI->getNumRegs(), false);
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BC.MIB->getWrittenRegs(Inst, WrittenRegs);
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getCallerSavedRegs(Inst, WrittenRegs, BC);
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if (BC.MIB->isRep(Inst))
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BC.MIB->getRepRegs(WrittenRegs);
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return (!regIsUsed(Inst, Reg, BC) && WrittenRegs.test(Reg) &&
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!BC.MIB->isConditionalMove(Inst));
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}
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bool TailDuplication::regIsUsed(const MCInst &Inst, unsigned Reg,
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BinaryContext &BC) const {
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BitVector SrcRegs = BitVector(BC.MRI->getNumRegs(), false);
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BC.MIB->getSrcRegs(Inst, SrcRegs);
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SrcRegs &= BC.MIB->getAliases(Reg, true);
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return SrcRegs.any();
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}
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bool TailDuplication::isOverwrittenBeforeUsed(BinaryBasicBlock &StartBB,
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unsigned Reg) const {
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BinaryFunction *BF = StartBB.getFunction();
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BinaryContext &BC = BF->getBinaryContext();
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std::queue<BinaryBasicBlock *> Q;
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for (auto Itr = StartBB.succ_begin(); Itr != StartBB.succ_end(); ++Itr) {
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BinaryBasicBlock *NextBB = *Itr;
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Q.push(NextBB);
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}
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std::set<BinaryBasicBlock *> Visited;
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// Breadth first search through successive blocks and see if Reg is ever used
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// before its overwritten
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while (Q.size() > 0) {
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BinaryBasicBlock *CurrBB = Q.front();
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Q.pop();
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if (Visited.count(CurrBB))
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continue;
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Visited.insert(CurrBB);
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bool Overwritten = false;
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for (auto Itr = CurrBB->begin(); Itr != CurrBB->end(); ++Itr) {
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MCInst &Inst = *Itr;
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if (regIsUsed(Inst, Reg, BC))
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return false;
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if (regIsDefinitelyOverwritten(Inst, Reg, BC)) {
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Overwritten = true;
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break;
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}
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}
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if (Overwritten)
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continue;
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for (auto Itr = CurrBB->succ_begin(); Itr != CurrBB->succ_end(); ++Itr) {
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BinaryBasicBlock *NextBB = *Itr;
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Q.push(NextBB);
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}
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}
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return true;
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}
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void TailDuplication::constantAndCopyPropagate(
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BinaryBasicBlock &OriginalBB,
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std::vector<BinaryBasicBlock *> &BlocksToPropagate) {
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BinaryFunction *BF = OriginalBB.getFunction();
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BinaryContext &BC = BF->getBinaryContext();
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BlocksToPropagate.insert(BlocksToPropagate.begin(), &OriginalBB);
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// Iterate through the original instructions to find one to propagate
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for (auto Itr = OriginalBB.begin(); Itr != OriginalBB.end(); ++Itr) {
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MCInst &OriginalInst = *Itr;
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// It must be a non conditional
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if (BC.MIB->isConditionalMove(OriginalInst))
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continue;
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// Move immediate or move register
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if ((!BC.MII->get(OriginalInst.getOpcode()).isMoveImmediate() ||
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!OriginalInst.getOperand(1).isImm()) &&
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(!BC.MII->get(OriginalInst.getOpcode()).isMoveReg() ||
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!OriginalInst.getOperand(1).isReg()))
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continue;
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// True if this is constant propagation and not copy propagation
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bool ConstantProp = BC.MII->get(OriginalInst.getOpcode()).isMoveImmediate();
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// The Register to replaced
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unsigned Reg = OriginalInst.getOperand(0).getReg();
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// True if the register to replace was replaced everywhere it was used
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bool ReplacedEverywhere = true;
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// True if the register was definitely overwritten
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bool Overwritten = false;
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// True if the register to replace and the register to replace with (for
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// copy propagation) has not been overwritten and is still usable
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bool RegsActive = true;
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// Iterate through successor blocks and through their instructions
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for (BinaryBasicBlock *NextBB : BlocksToPropagate) {
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for (auto PropagateItr =
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((NextBB == &OriginalBB) ? Itr + 1 : NextBB->begin());
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PropagateItr < NextBB->end(); ++PropagateItr) {
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MCInst &PropagateInst = *PropagateItr;
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if (regIsUsed(PropagateInst, Reg, BC)) {
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bool Replaced = false;
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// If both registers are active for copy propagation or the register
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// to replace is active for constant propagation
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if (RegsActive) {
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// Set Replaced and so ReplacedEverwhere to false if it cannot be
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// replaced (no replacing that opcode, Register is src and dest)
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if (ConstantProp) {
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Replaced = BC.MIB->replaceRegWithImm(
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PropagateInst, Reg, OriginalInst.getOperand(1).getImm());
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} else {
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Replaced = BC.MIB->replaceRegWithReg(
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PropagateInst, Reg, OriginalInst.getOperand(1).getReg());
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}
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}
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ReplacedEverywhere = ReplacedEverywhere && Replaced;
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}
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// For copy propagation, make sure no propagation happens after the
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// register to replace with is overwritten
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if (!ConstantProp &&
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regIsPossiblyOverwritten(PropagateInst,
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OriginalInst.getOperand(1).getReg(), BC)) {
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RegsActive = false;
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}
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// Make sure no propagation happens after the register to replace is
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// overwritten
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if (regIsPossiblyOverwritten(PropagateInst, Reg, BC)) {
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RegsActive = false;
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}
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// Record if the register to replace is overwritten
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if (regIsDefinitelyOverwritten(PropagateInst, Reg, BC)) {
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Overwritten = true;
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break;
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}
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}
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if (Overwritten)
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break;
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}
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// If the register was replaced everwhere and it was overwritten in either
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// one of the iterated through blocks or one of the successor blocks, delete
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// the original move instruction
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if (ReplacedEverywhere &&
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(Overwritten ||
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isOverwrittenBeforeUsed(
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*BlocksToPropagate[BlocksToPropagate.size() - 1], Reg))) {
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// If both registers are active for copy propagation or the register
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// to replace is active for constant propagation
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StaticInstructionDeletionCount++;
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DynamicInstructionDeletionCount += OriginalBB.getExecutionCount();
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Itr = std::prev(OriginalBB.eraseInstruction(Itr));
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}
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}
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}
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bool TailDuplication::isInCacheLine(const BinaryBasicBlock &BB,
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const BinaryBasicBlock &Succ) const {
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if (&BB == &Succ)
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@ -123,7 +296,7 @@ TailDuplication::aggressiveCodeToDuplicate(BinaryBasicBlock &BB) const {
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return BlocksToDuplicate;
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}
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void TailDuplication::tailDuplicate(
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std::vector<BinaryBasicBlock *> TailDuplication::tailDuplicate(
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BinaryBasicBlock &BB,
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const std::vector<BinaryBasicBlock *> &BlocksToDuplicate) const {
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BinaryFunction *BF = BB.getFunction();
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@ -149,6 +322,7 @@ void TailDuplication::tailDuplicate(
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LastDuplicatedBB->removeSuccessor(LastDuplicatedBB->getSuccessor());
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std::vector<std::unique_ptr<BinaryBasicBlock>> DuplicatedBlocks;
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std::vector<BinaryBasicBlock *> DuplicatedBlocksToReturn;
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for (BinaryBasicBlock *CurrBB : BlocksToDuplicate) {
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DuplicatedBlocks.emplace_back(
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@ -161,6 +335,8 @@ void TailDuplication::tailDuplicate(
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std::max((uint64_t)1, CurrBB->getExecutionCount()));
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LastDuplicatedBB->addSuccessor(NewBB, LastBI);
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DuplicatedBlocksToReturn.push_back(NewBB);
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// As long as its not the first block, adjust both original and duplicated
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// to what they should be
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if (LastDuplicatedBB != &BB) {
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@ -183,6 +359,8 @@ void TailDuplication::tailDuplicate(
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LastDuplicatedBB->adjustExecutionCount(ExecutionCountRatio);
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BF->insertBasicBlocks(&BB, std::move(DuplicatedBlocks));
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return DuplicatedBlocksToReturn;
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}
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void TailDuplication::runOnFunction(BinaryFunction &Function) {
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@ -222,7 +400,15 @@ void TailDuplication::runOnFunction(BinaryFunction &Function) {
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if (BlocksToDuplicate.size() > 0) {
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PossibleDuplications++;
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PossibleDuplicationsDynamicCount += BB->getExecutionCount();
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tailDuplicate(*BB, BlocksToDuplicate);
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std::vector<BinaryBasicBlock *> DuplicatedBlocks =
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tailDuplicate(*BB, BlocksToDuplicate);
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constantAndCopyPropagate(*BB, DuplicatedBlocks);
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BinaryBasicBlock *FirstBB = BlocksToDuplicate[0];
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if (FirstBB->pred_size() == 1) {
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BinaryBasicBlock *PredBB = *FirstBB->pred_begin();
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if (PredBB->succ_size() == 1)
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constantAndCopyPropagate(*PredBB, BlocksToDuplicate);
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}
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}
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}
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}
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@ -230,6 +416,8 @@ void TailDuplication::runOnFunction(BinaryFunction &Function) {
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void TailDuplication::runOnFunctions(BinaryContext &BC) {
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for (auto &It : BC.getBinaryFunctions()) {
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BinaryFunction &Function = It.second;
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if (Function.isIgnored())
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continue;
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runOnFunction(Function);
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}
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@ -247,6 +435,10 @@ void TailDuplication::runOnFunctions(BinaryContext &BC) {
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<< format("%.1f", ((float)PossibleDuplicationsDynamicCount * 100.0f) /
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AllBlocksDynamicCount)
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<< "%\n";
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outs() << "BOLT-INFO: tail duplication static propagation deletions: "
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<< StaticInstructionDeletionCount << "\n";
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outs() << "BOLT-INFO: tail duplication dynamic propagation deletions: "
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<< DynamicInstructionDeletionCount << "\n"; //
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}
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} // end namespace bolt
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@ -57,12 +57,42 @@ class TailDuplication : public BinaryFunctionPass {
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/// Record the execution count of all blocks.
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uint64_t AllBlocksDynamicCount = 0;
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/// Record the number of instructions deleted because of propagation
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uint64_t StaticInstructionDeletionCount = 0;
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/// Record the number of instructions deleted because of propagation
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uint64_t DynamicInstructionDeletionCount = 0;
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/// Sets Regs with the caller saved registers
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void getCallerSavedRegs(const MCInst &Inst, BitVector &Regs,
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BinaryContext &BC) const;
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/// Returns true if Reg is possibly overwritten by Inst
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bool regIsPossiblyOverwritten(const MCInst &Inst, unsigned Reg,
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BinaryContext &BC) const;
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/// Returns true if Reg is definitely overwritten by Inst
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bool regIsDefinitelyOverwritten(const MCInst &Inst, unsigned Reg,
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BinaryContext &BC) const;
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/// Returns true if Reg is used by Inst
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bool regIsUsed(const MCInst &Inst, unsigned Reg, BinaryContext &BC) const;
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/// Returns true if Reg is overwritten before its used by StartBB's sucessors
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bool isOverwrittenBeforeUsed(BinaryBasicBlock &StartBB, unsigned Reg) const;
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/// Constant and Copy Propagate for the block formed by OriginalBB and
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/// BlocksToPropagate
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void
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constantAndCopyPropagate(BinaryBasicBlock &OriginalBB,
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std::vector<BinaryBasicBlock *> &BlocksToPropagate);
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/// True if Succ is in the same cache line as BB (approximately)
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bool isInCacheLine(const BinaryBasicBlock &BB,
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const BinaryBasicBlock &Succ) const;
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/// Duplicates BlocksToDuplicate and places them after BB.
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void
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std::vector<BinaryBasicBlock *>
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tailDuplicate(BinaryBasicBlock &BB,
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const std::vector<BinaryBasicBlock *> &BlocksToDuplicate) const;
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@ -436,6 +436,10 @@ public:
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return false;
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}
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bool isRep(const MCInst &Inst) const override {
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return Inst.getFlags() == X86::IP_HAS_REPEAT;
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}
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bool deleteREPPrefix(MCInst &Inst) const override {
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if (Inst.getFlags() == X86::IP_HAS_REPEAT) {
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Inst.setFlags(0);
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@ -1169,6 +1173,10 @@ public:
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Regs |= getAliases(X86::RCX);
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}
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void getRepRegs(BitVector &Regs) const override {
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Regs |= getAliases(X86::RCX);
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}
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MCPhysReg getAliasSized(MCPhysReg Reg, uint8_t Size) const override {
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switch (Reg) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: case X86::AH:
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@ -1207,7 +1215,19 @@ public:
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case 2: return X86::CX; case 1: return X86::CL;
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default: llvm_unreachable("Unexpected size");
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}
|
||||
case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
|
||||
case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL:
|
||||
switch (Size) {
|
||||
case 8: return X86::RSP; case 4: return X86::ESP;
|
||||
case 2: return X86::SP; case 1: return X86::SPL;
|
||||
default: llvm_unreachable("Unexpected size");
|
||||
}
|
||||
case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL:
|
||||
switch (Size) {
|
||||
case 8: return X86::RBP; case 4: return X86::EBP;
|
||||
case 2: return X86::BP; case 1: return X86::BPL;
|
||||
default: llvm_unreachable("Unexpected size");
|
||||
}
|
||||
case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
|
||||
switch (Size) {
|
||||
case 8: return X86::R8; case 4: return X86::R8D;
|
||||
case 2: return X86::R8W; case 1: return X86::R8B;
|
||||
|
|
@ -2938,6 +2958,248 @@ public:
|
|||
return true;
|
||||
}
|
||||
|
||||
bool replaceRegWithImm(MCInst &Inst, unsigned Register,
|
||||
int64_t Imm) const override {
|
||||
|
||||
enum CheckSignExt : uint8_t {
|
||||
NOCHECK = 0,
|
||||
CHECK8,
|
||||
CHECK32,
|
||||
};
|
||||
|
||||
using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>;
|
||||
struct InstInfo {
|
||||
// Size in bytes that Inst loads from memory.
|
||||
uint8_t DataSize;
|
||||
|
||||
// True when the target operand has to be duplicated because the opcode
|
||||
// expects a LHS operand.
|
||||
bool HasLHS;
|
||||
|
||||
// List of checks and corresponding opcodes to be used. We try to use the
|
||||
// smallest possible immediate value when various sizes are available,
|
||||
// hence we may need to check whether a larger constant fits in a smaller
|
||||
// immediate.
|
||||
CheckList Checks;
|
||||
};
|
||||
|
||||
InstInfo I;
|
||||
|
||||
switch (Inst.getOpcode()) {
|
||||
default: {
|
||||
switch (getPushSize(Inst)) {
|
||||
|
||||
case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSHi16}}}; break;
|
||||
case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSHi32}}}; break;
|
||||
case 8: I = {8, false, {{CHECK8, X86::PUSH64i8},
|
||||
{CHECK32, X86::PUSH64i32},
|
||||
{NOCHECK, Inst.getOpcode()}}}; break;
|
||||
default: return false;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// MOV
|
||||
case X86::MOV8rr: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break;
|
||||
case X86::MOV16rr: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break;
|
||||
case X86::MOV32rr: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break;
|
||||
case X86::MOV64rr: I = {8, false, {{CHECK32, X86::MOV64ri32},
|
||||
{NOCHECK, X86::MOV64ri}}}; break;
|
||||
|
||||
case X86::MOV8mr: I = {1, false, {{NOCHECK, X86::MOV8mi}}}; break;
|
||||
case X86::MOV16mr: I = {2, false, {{NOCHECK, X86::MOV16mi}}}; break;
|
||||
case X86::MOV32mr: I = {4, false, {{NOCHECK, X86::MOV32mi}}}; break;
|
||||
case X86::MOV64mr: I = {8, false, {{CHECK32, X86::MOV64mi32},
|
||||
{NOCHECK, X86::MOV64mr}}}; break;
|
||||
|
||||
// MOVZX
|
||||
case X86::MOVZX16rr8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break;
|
||||
case X86::MOVZX32rr8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break;
|
||||
case X86::MOVZX32rr16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break;
|
||||
|
||||
// CMP
|
||||
case X86::CMP8rr: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break;
|
||||
case X86::CMP16rr: I = {2, false, {{CHECK8, X86::CMP16ri8},
|
||||
{NOCHECK, X86::CMP16ri}}}; break;
|
||||
case X86::CMP32rr: I = {4, false, {{CHECK8, X86::CMP32ri8},
|
||||
{NOCHECK, X86::CMP32ri}}}; break;
|
||||
case X86::CMP64rr: I = {8, false, {{CHECK8, X86::CMP64ri8},
|
||||
{CHECK32, X86::CMP64ri32},
|
||||
{NOCHECK, X86::CMP64rr}}}; break;
|
||||
|
||||
// TEST
|
||||
case X86::TEST8rr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break;
|
||||
case X86::TEST16rr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break;
|
||||
case X86::TEST32rr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break;
|
||||
case X86::TEST64rr: I = {8, false, {{CHECK32, X86::TEST64ri32},
|
||||
{NOCHECK, X86::TEST64rr}}}; break;
|
||||
|
||||
// ADD
|
||||
case X86::ADD8rr: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break;
|
||||
case X86::ADD16rr: I = {2, true, {{CHECK8, X86::ADD16ri8},
|
||||
{NOCHECK, X86::ADD16ri}}}; break;
|
||||
case X86::ADD32rr: I = {4, true, {{CHECK8, X86::ADD32ri8},
|
||||
{NOCHECK, X86::ADD32ri}}}; break;
|
||||
case X86::ADD64rr: I = {8, true, {{CHECK8, X86::ADD64ri8},
|
||||
{CHECK32, X86::ADD64ri32},
|
||||
{NOCHECK, X86::ADD64rr}}}; break;
|
||||
|
||||
// SUB
|
||||
case X86::SUB8rr: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break;
|
||||
case X86::SUB16rr: I = {2, true, {{CHECK8, X86::SUB16ri8},
|
||||
{NOCHECK, X86::SUB16ri}}}; break;
|
||||
case X86::SUB32rr: I = {4, true, {{CHECK8, X86::SUB32ri8},
|
||||
{NOCHECK, X86::SUB32ri}}}; break;
|
||||
case X86::SUB64rr: I = {8, true, {{CHECK8, X86::SUB64ri8},
|
||||
{CHECK32, X86::SUB64ri32},
|
||||
{NOCHECK, X86::SUB64rr}}}; break;
|
||||
|
||||
// AND
|
||||
case X86::AND8rr: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break;
|
||||
case X86::AND16rr: I = {2, true, {{CHECK8, X86::AND16ri8},
|
||||
{NOCHECK, X86::AND16ri}}}; break;
|
||||
case X86::AND32rr: I = {4, true, {{CHECK8, X86::AND32ri8},
|
||||
{NOCHECK, X86::AND32ri}}}; break;
|
||||
case X86::AND64rr: I = {8, true, {{CHECK8, X86::AND64ri8},
|
||||
{CHECK32, X86::AND64ri32},
|
||||
{NOCHECK, X86::AND64rr}}}; break;
|
||||
|
||||
// OR
|
||||
case X86::OR8rr: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break;
|
||||
case X86::OR16rr: I = {2, true, {{CHECK8, X86::OR16ri8},
|
||||
{NOCHECK, X86::OR16ri}}}; break;
|
||||
case X86::OR32rr: I = {4, true, {{CHECK8, X86::OR32ri8},
|
||||
{NOCHECK, X86::OR32ri}}}; break;
|
||||
case X86::OR64rr: I = {8, true, {{CHECK8, X86::OR64ri8},
|
||||
{CHECK32, X86::OR64ri32},
|
||||
{NOCHECK, X86::OR64rr}}}; break;
|
||||
|
||||
// XOR
|
||||
case X86::XOR8rr: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break;
|
||||
case X86::XOR16rr: I = {2, true, {{CHECK8, X86::XOR16ri8},
|
||||
{NOCHECK, X86::XOR16ri}}}; break;
|
||||
case X86::XOR32rr: I = {4, true, {{CHECK8, X86::XOR32ri8},
|
||||
{NOCHECK, X86::XOR32ri}}}; break;
|
||||
case X86::XOR64rr: I = {8, true, {{CHECK8, X86::XOR64ri8},
|
||||
{CHECK32, X86::XOR64ri32},
|
||||
{NOCHECK, X86::XOR64rr}}}; break;
|
||||
}
|
||||
|
||||
// Compute the new opcode.
|
||||
unsigned NewOpcode = 0;
|
||||
for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) {
|
||||
NewOpcode = Check.second;
|
||||
if (Check.first == NOCHECK)
|
||||
break;
|
||||
if (Check.first == CHECK8 && Imm >= std::numeric_limits<int8_t>::min() &&
|
||||
Imm <= std::numeric_limits<int8_t>::max())
|
||||
break;
|
||||
if (Check.first == CHECK32 &&
|
||||
Imm >= std::numeric_limits<int32_t>::min() &&
|
||||
Imm <= std::numeric_limits<int32_t>::max())
|
||||
break;
|
||||
}
|
||||
if (NewOpcode == Inst.getOpcode())
|
||||
return false;
|
||||
|
||||
const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode());
|
||||
|
||||
unsigned NumFound = 0;
|
||||
for (unsigned Index = InstDesc.getNumDefs() + (I.HasLHS ? 1 : 0),
|
||||
E = InstDesc.getNumOperands(); Index != E; ++Index) {
|
||||
if (Inst.getOperand(Index).isReg() &&
|
||||
Inst.getOperand(Index).getReg() == Register)
|
||||
NumFound++;
|
||||
}
|
||||
|
||||
if (NumFound != 1)
|
||||
return false;
|
||||
|
||||
// Iterate backwards to replace the src register before the src/dest
|
||||
// register as in AND, ADD, and SUB Only iterate through src operands that
|
||||
// arent also dest operands
|
||||
for (unsigned Index = InstDesc.getNumOperands() - 1,
|
||||
E = InstDesc.getNumDefs() + (I.HasLHS ? 0 : -1);
|
||||
Index != E; --Index) {
|
||||
if (!Inst.getOperand(Index).isReg() ||
|
||||
Inst.getOperand(Index).getReg() != Register)
|
||||
continue;
|
||||
MCOperand NewOperand = MCOperand::createImm(Imm);
|
||||
Inst.getOperand(Index) = NewOperand;
|
||||
break;
|
||||
}
|
||||
|
||||
Inst.setOpcode(NewOpcode);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool replaceRegWithReg(MCInst &Inst, unsigned ToReplace,
|
||||
unsigned ReplaceWith) const override {
|
||||
|
||||
// Get the HasLHS value so that iteration can be done
|
||||
bool HasLHS;
|
||||
if (isAND(Inst.getOpcode()) || isADD(Inst.getOpcode()) || isSUB(Inst)) {
|
||||
HasLHS = true;
|
||||
} else if (isPop(Inst) || isPush(Inst) || isCMP(Inst.getOpcode()) ||
|
||||
isTEST(Inst.getOpcode())) {
|
||||
HasLHS = false;
|
||||
} else {
|
||||
switch (Inst.getOpcode()) {
|
||||
case X86::MOV8rr:
|
||||
case X86::MOV8rm:
|
||||
case X86::MOV8mr:
|
||||
case X86::MOV8ri:
|
||||
case X86::MOV16rr:
|
||||
case X86::MOV16rm:
|
||||
case X86::MOV16mr:
|
||||
case X86::MOV16ri:
|
||||
case X86::MOV32rr:
|
||||
case X86::MOV32rm:
|
||||
case X86::MOV32mr:
|
||||
case X86::MOV32ri:
|
||||
case X86::MOV64rr:
|
||||
case X86::MOV64rm:
|
||||
case X86::MOV64mr:
|
||||
case X86::MOV64ri:
|
||||
case X86::MOVZX16rr8:
|
||||
case X86::MOVZX32rr8:
|
||||
case X86::MOVZX32rr16:
|
||||
case X86::MOVSX32rm8:
|
||||
case X86::MOVSX32rr8:
|
||||
case X86::MOVSX64rm32:
|
||||
case X86::LEA64r:
|
||||
HasLHS = false;
|
||||
break;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode());
|
||||
|
||||
bool FoundOne = false;
|
||||
|
||||
// Iterate only through src operands that arent also dest operands
|
||||
for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0),
|
||||
E = InstDesc.getNumOperands();
|
||||
Index != E; ++Index) {
|
||||
BitVector RegAliases = getAliases(ToReplace, true);
|
||||
if (!Inst.getOperand(Index).isReg() ||
|
||||
!RegAliases.test(Inst.getOperand(Index).getReg()))
|
||||
continue;
|
||||
// Resize register if needed
|
||||
unsigned SizedReplaceWith = getAliasSized(
|
||||
ReplaceWith, getRegSize(Inst.getOperand(Index).getReg()));
|
||||
MCOperand NewOperand = MCOperand::createReg(SizedReplaceWith);
|
||||
Inst.getOperand(Index) = NewOperand;
|
||||
FoundOne = true;
|
||||
}
|
||||
|
||||
// Return true if at least one operand was replaced
|
||||
return FoundOne;
|
||||
}
|
||||
|
||||
bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
|
||||
MCContext *Ctx) const override {
|
||||
Inst.setOpcode(X86::JMP_1);
|
||||
|
|
@ -3081,6 +3343,12 @@ public:
|
|||
Seq.emplace_back(Inst);
|
||||
}
|
||||
|
||||
bool isConditionalMove(const MCInst &Inst) const override {
|
||||
unsigned OpCode = Inst.getOpcode();
|
||||
return (OpCode == X86::CMOV16rr || OpCode == X86::CMOV32rr ||
|
||||
OpCode == X86::CMOV64rr);
|
||||
}
|
||||
|
||||
bool isBranchOnMem(const MCInst &Inst) const override {
|
||||
unsigned OpCode = Inst.getOpcode();
|
||||
if (OpCode == X86::CALL64m || (OpCode == X86::JMP32m && isTailCall(Inst)) ||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
# REQUIRES: system-linux
|
||||
|
||||
# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown \
|
||||
# RUN: %s -o %t.o
|
||||
# RUN: link_fdata %s %t.o %t.fdata
|
||||
# RUN: %host_cc %cflags %t.o -o %t.exe -Wl,-q
|
||||
# RUN: llvm-bolt %t.exe -data %t.fdata -reorder-blocks=cache+ -print-finalized \
|
||||
# RUN: -tail-duplication -tail-duplication-minimum-offset 1 -o %t.out | FileCheck %s
|
||||
# RUN: %t.exe; echo $?
|
||||
# RUN: %t.out; echo $?
|
||||
|
||||
# FDATA: 1 main 14 1 main #.BB2# 0 10
|
||||
# FDATA: 1 main 16 1 main #.BB2# 0 20
|
||||
# CHECK: tail duplication possible duplications: 1
|
||||
# CHECK: BB Layout : .LBB00, .Ltail-dup0, .Ltmp0, .Ltmp1
|
||||
# CHECK-NOT: mov $0x2, %rbx
|
||||
|
||||
.text
|
||||
.globl main
|
||||
.type main, %function
|
||||
.size main, .Lend-main
|
||||
main:
|
||||
mov $0x2, %rbx
|
||||
mov $0x1, %rdi
|
||||
inc %rdi
|
||||
mov %rdi, %rsi
|
||||
jmp .BB2
|
||||
.BB1:
|
||||
mov $0x9, %rbx
|
||||
.BB2:
|
||||
mov %rbx, %rax
|
||||
mov $0x5, %rbx
|
||||
add %rsi, %rax
|
||||
jmp .BB4
|
||||
.BB3:
|
||||
mov $0x9, %rbx
|
||||
.BB4:
|
||||
mov $0xa, %rsi
|
||||
add %rbx, %rax
|
||||
add %rsi, %rax
|
||||
.BB5:
|
||||
retq
|
||||
.Lend:
|
||||
Loading…
Reference in New Issue