forked from OSchip/llvm-project
AMDGPU: Add a few more tail call tests
Add some cases I noticed were missing when porting to GlobalISel. The cases that required any argument splitting did not work at first.
This commit is contained in:
Matt Arsenault
parent
6e88539ab1
commit
ef5f0adecd
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@ -302,5 +302,171 @@ entry:
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ret i32 %ret
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}
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declare hidden void @void_fastcc_multi_byval(i32 %a, [3 x i32] addrspace(5)* byval([3 x i32]) align 16, [2 x i64] addrspace(5)* byval([2 x i64]))
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; GCN-LABEL: {{^}}sibling_call_fastcc_multi_byval:
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; GCN-DAG: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:144
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:148
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:152
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:4{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:8{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:160
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:164
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:168
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:172
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:16{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:20{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:24{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:28{{$}}
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; GCN: s_setpc_b64 [[TARGET_ADDR]]
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define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
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entry:
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%alloca0 = alloca [3 x i32], align 16, addrspace(5)
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%alloca1 = alloca [2 x i64], align 8, addrspace(5)
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store [3 x i32] [i32 9, i32 9, i32 9], [3 x i32] addrspace(5)* %alloca0
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store [2 x i64] zeroinitializer, [2 x i64] addrspace(5)* %alloca1
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tail call fastcc void @void_fastcc_multi_byval(i32 %a, [3 x i32] addrspace(5)* byval([3 x i32]) %alloca0, [2 x i64] addrspace(5)* byval([2 x i64]) %alloca1)
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ret void
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}
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declare hidden void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)* byval([3 x i32]) align 16, [32 x i32], i32)
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; Callee has a byval and non-byval stack passed argument
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; GCN-LABEL: {{^}}sibling_call_byval_and_stack_passed:
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; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:144
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:148
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:152
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:4{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:8{{$}}
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; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:12
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; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:16
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; GCN: v_mov_b32_e32 v0, 0
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; GCN: v_mov_b32_e32 v30, 0
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; GCN: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+[0-9]+]]
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64 [[TARGET_ADDR]]
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define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64 x i32]) #1 {
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entry:
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%alloca = alloca [3 x i32], align 16, addrspace(5)
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store [3 x i32] [i32 9, i32 9, i32 9], [3 x i32] addrspace(5)* %alloca
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tail call fastcc void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)* byval([3 x i32]) %alloca, [32 x i32] zeroinitializer, i32 %stack.out.arg)
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ret void
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}
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declare hidden fastcc i64 @i64_fastcc_i64(i64 %arg0)
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; GCN-LABEL: {{^}}sibling_call_i64_fastcc_i64:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc i64 @sibling_call_i64_fastcc_i64(i64 %a) #1 {
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entry:
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%ret = tail call fastcc i64 @i64_fastcc_i64(i64 %a)
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ret i64 %ret
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}
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declare hidden fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %arg0)
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; GCN-LABEL: {{^}}sibling_call_p1i8_fastcc_p1i8:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc i8 addrspace(1)* @sibling_call_p1i8_fastcc_p1i8(i8 addrspace(1)* %a) #1 {
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entry:
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%ret = tail call fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %a)
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ret i8 addrspace(1)* %ret
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}
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declare hidden fastcc i16 @i16_fastcc_i16(i16 %arg0)
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; GCN-LABEL: {{^}}sibling_call_i16_fastcc_i16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
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entry:
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%ret = tail call fastcc i16 @i16_fastcc_i16(i16 %a)
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ret i16 %ret
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}
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declare hidden fastcc half @f16_fastcc_f16(half %arg0)
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; GCN-LABEL: {{^}}sibling_call_f16_fastcc_f16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
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entry:
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%ret = tail call fastcc half @f16_fastcc_f16(half %a)
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ret half %ret
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}
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declare hidden fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %arg0)
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; GCN-LABEL: {{^}}sibling_call_v3i16_fastcc_v3i16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc <3 x i16> @sibling_call_v3i16_fastcc_v3i16(<3 x i16> %a) #1 {
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entry:
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%ret = tail call fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %a)
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ret <3 x i16> %ret
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}
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declare hidden fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %arg0)
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; GCN-LABEL: {{^}}sibling_call_v4i16_fastcc_v4i16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc <4 x i16> @sibling_call_v4i16_fastcc_v4i16(<4 x i16> %a) #1 {
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entry:
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%ret = tail call fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %a)
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ret <4 x i16> %ret
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}
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declare hidden fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %arg0)
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; GCN-LABEL: {{^}}sibling_call_v2i64_fastcc_v2i64:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc <2 x i64> @sibling_call_v2i64_fastcc_v2i64(<2 x i64> %a) #1 {
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entry:
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%ret = tail call fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %a)
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ret <2 x i64> %ret
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noinline }
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