From ef5debac4302cd479ddd9e784a5b5acc8c2b9804 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 13 Jan 2020 12:01:56 +0000 Subject: [PATCH] [SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD::SHL support As mentioned on D72573 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +++ llvm/test/CodeGen/X86/combine-shl.ll | 5 ++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 4fa438a2795d..591805971305 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2834,6 +2834,9 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, Known.One <<= Shift; // Low bits are known zero. Known.Zero.setLowBits(Shift); + } else if (const APInt *ShMinAmt = getValidMinimumShiftAmountConstant(Op)) { + // Minimum shift low bits are known zero. + Known.Zero.setLowBits(ShMinAmt->getZExtValue()); } else { // No matter the shift amount, the trailing zeros will stay zero. Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll index 40971dc3eafe..0052f51c5427 100644 --- a/llvm/test/CodeGen/X86/combine-shl.ll +++ b/llvm/test/CodeGen/X86/combine-shl.ll @@ -834,7 +834,6 @@ define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) { } ; fold (add (shl x, c1), c2) -> (or (shl x, c1), c2) -; TODO: Handle minimum shift value case define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) { ; SSE2-LABEL: combine_vec_add_shl_nonsplat: ; SSE2: # %bb.0: @@ -846,7 +845,7 @@ define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) { ; SSE2-NEXT: pmuludq %xmm2, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0 +; SSE2-NEXT: por {{.*}}(%rip), %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: combine_vec_add_shl_nonsplat: @@ -859,7 +858,7 @@ define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) { ; AVX: # %bb.0: ; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3] -; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = shl <4 x i32> %a0, %2 = add <4 x i32> %1,