maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD::SHL support 

As mentioned on D72573
This commit is contained in:
Simon Pilgrim 2020-01-13 12:01:56 +00:00
parent 7efc7ca8ed
commit ef5debac43
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2834,6 +2834,9 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known.One <<= Shift;
// Low bits are known zero.
Known.Zero.setLowBits(Shift);
} else if (const APInt *ShMinAmt = getValidMinimumShiftAmountConstant(Op)) {
// Minimum shift low bits are known zero.
Known.Zero.setLowBits(ShMinAmt->getZExtValue());
} else {
// No matter the shift amount, the trailing zeros will stay zero.
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);

5
llvm/test/CodeGen/X86/combine-shl.ll
View File

@ -834,7 +834,6 @@ define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) {
}
; fold (add (shl x, c1), c2) -> (or (shl x, c1), c2)
; TODO: Handle minimum shift value case
define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) {
; SSE2-LABEL: combine_vec_add_shl_nonsplat:
; SSE2: # %bb.0:
@ -846,7 +845,7 @@ define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) {
; SSE2-NEXT: pmuludq %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0
; SSE2-NEXT: por {{.*}}(%rip), %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_add_shl_nonsplat:
@ -859,7 +858,7 @@ define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) {
; AVX: # %bb.0:
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3]
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = shl <4 x i32> %a0, <i32 2, i32 3, i32 4, i32 5>
%2 = add <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>