forked from OSchip/llvm-project
Add "blocked" heuristic to the Hexagon MI scheduler.
Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
This commit is contained in:
Sergei Larin
parent
ca8b950317
commit
ef4cc11cf9
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@ -190,6 +190,9 @@ void VLIWMachineScheduler::initRegPressure() {
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std::vector<unsigned> RegionPressure = RPTracker.getPressure().MaxSetPressure;
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for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
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unsigned Limit = TRI->getRegPressureSetLimit(i);
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DEBUG(dbgs() << TRI->getRegPressureSetName(i)
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<< "Limit " << Limit
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<< " Actual " << RegionPressure[i] << "\n");
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if (RegionPressure[i] > Limit)
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RegionCriticalPSets.push_back(PressureElement(i, 0));
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}
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@ -199,11 +202,6 @@ void VLIWMachineScheduler::initRegPressure() {
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RegionCriticalPSets[i].PSetID) << " ";
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dbgs() << "\n");
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// Reset resource state.
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TopResourceModel->resetPacketState();
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TopResourceModel->resetDFA();
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BotResourceModel->resetPacketState();
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BotResourceModel->resetDFA();
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TotalPackets = 0;
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}
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@ -264,13 +262,15 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
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}
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/// Keep track of available resources.
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void VLIWResourceModel::reserveResources(SUnit *SU) {
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bool VLIWResourceModel::reserveResources(SUnit *SU) {
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bool startNewCycle = false;
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// If this SU does not fit in the packet
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// start a new one.
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if (!isResourceAvailable(SU)) {
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ResourcesModel->clearResources();
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Packet.clear();
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TotalPackets++;
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startNewCycle = true;
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}
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switch (SU->getInstr()->getOpcode()) {
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@ -295,7 +295,8 @@ void VLIWResourceModel::reserveResources(SUnit *SU) {
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DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n");
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for (unsigned i = 0, e = Packet.size(); i != e; ++i) {
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DEBUG(dbgs() << "\t[" << i << "] SU(");
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DEBUG(dbgs() << Packet[i]->NodeNum << ")\n");
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DEBUG(dbgs() << Packet[i]->NodeNum << ")\t");
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DEBUG(Packet[i]->getInstr()->dump());
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}
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#endif
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@ -305,7 +306,10 @@ void VLIWResourceModel::reserveResources(SUnit *SU) {
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ResourcesModel->clearResources();
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Packet.clear();
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TotalPackets++;
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startNewCycle = true;
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}
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return startNewCycle;
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}
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// Release all DAG roots for scheduling.
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@ -352,6 +356,17 @@ void VLIWMachineScheduler::schedule() {
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// Initialize top/bottom trackers after computing region pressure.
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initRegPressure();
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// To view Height/Depth correctly, they should be accessed at least once.
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DEBUG(unsigned maxH = 0;
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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if (SUnits[su].getHeight() > maxH)
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maxH = SUnits[su].getHeight();
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dbgs() << "Max Height " << maxH << "\n";);
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DEBUG(unsigned maxD = 0;
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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if (SUnits[su].getDepth() > maxD)
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maxD = SUnits[su].getDepth();
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dbgs() << "Max Depth " << maxD << "\n";);
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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@ -390,13 +405,9 @@ void VLIWMachineScheduler::schedule() {
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assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
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updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
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// Update DFA state.
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TopResourceModel->reserveResources(SU);
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// Release dependent instructions for scheduling.
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releaseSuccessors(SU);
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}
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else {
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} else {
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assert(SU->isBottomReady() && "node still has unscheduled dependencies");
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MachineBasicBlock::iterator priorII =
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priorNonDebug(CurrentBottom, CurrentTop);
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@ -415,9 +426,6 @@ void VLIWMachineScheduler::schedule() {
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assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
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updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
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// Update DFA state.
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BotResourceModel->reserveResources(SU);
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// Release dependent instructions for scheduling.
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releasePredecessors(SU);
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}
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@ -426,9 +434,6 @@ void VLIWMachineScheduler::schedule() {
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}
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assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
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DEBUG(dbgs() << "Final schedule has " << TopResourceModel->getTotalPackets() +
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BotResourceModel->getTotalPackets()<< "packets.\n");
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placeDebugValues();
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}
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@ -465,6 +470,9 @@ void ConvergingVLIWScheduler::initialize(VLIWMachineScheduler *dag) {
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Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
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Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
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Top.ResourceModel = new VLIWResourceModel(TM);
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Bot.ResourceModel = new VLIWResourceModel(TM);
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assert((!ForceTopDown || !ForceBottomUp) &&
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"-misched-topdown incompatible with -misched-bottomup");
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}
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@ -553,8 +561,7 @@ void ConvergingVLIWScheduler::SchedBoundary::bumpCycle() {
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if (!HazardRec->isEnabled()) {
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// Bypass HazardRec virtual calls.
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CurrCycle = NextCycle;
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}
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else {
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} else {
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// Bypass getHazardType calls in case of long latency.
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for (; CurrCycle != NextCycle; ++CurrCycle) {
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if (isTop())
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@ -571,6 +578,7 @@ void ConvergingVLIWScheduler::SchedBoundary::bumpCycle() {
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/// Move the boundary of scheduled code by one SUnit.
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void ConvergingVLIWScheduler::SchedBoundary::bumpNode(SUnit *SU) {
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bool startNewCycle = false;
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// Update the reservation table.
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if (HazardRec->isEnabled()) {
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@ -581,13 +589,20 @@ void ConvergingVLIWScheduler::SchedBoundary::bumpNode(SUnit *SU) {
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}
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HazardRec->EmitInstruction(SU);
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}
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// Update DFA model.
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startNewCycle = ResourceModel->reserveResources(SU);
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// Check the instruction group dispatch limit.
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// TODO: Check if this SU must end a dispatch group.
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IssueCount += DAG->getNumMicroOps(SU->getInstr());
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if (IssueCount >= DAG->getIssueWidth()) {
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if (startNewCycle) {
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DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');
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bumpCycle();
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}
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else
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DEBUG(dbgs() << "*** IssueCount " << IssueCount
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<< " at cycle " << CurrCycle << '\n');
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}
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/// Release pending ready nodes in to the available queue. This makes them
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@ -648,8 +663,9 @@ SUnit *ConvergingVLIWScheduler::SchedBoundary::pickOnlyChoice() {
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}
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#ifndef NDEBUG
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void ConvergingVLIWScheduler::traceCandidate(const char *Label, const ReadyQueue &Q,
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SUnit *SU, PressureElement P) {
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void ConvergingVLIWScheduler::traceCandidate(const char *Label,
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const ReadyQueue &Q,
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SUnit *SU, PressureElement P) {
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dbgs() << Label << " " << Q.getName() << " ";
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if (P.isValid())
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dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
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@ -660,10 +676,48 @@ void ConvergingVLIWScheduler::traceCandidate(const char *Label, const ReadyQueue
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}
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#endif
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/// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor
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/// of SU, return it, otherwise return null.
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static SUnit *getSingleUnscheduledPred(SUnit *SU) {
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SUnit *OnlyAvailablePred = 0;
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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SUnit &Pred = *I->getSUnit();
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if (!Pred.isScheduled) {
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// We found an available, but not scheduled, predecessor. If it's the
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// only one we have found, keep track of it... otherwise give up.
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if (OnlyAvailablePred && OnlyAvailablePred != &Pred)
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return 0;
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OnlyAvailablePred = &Pred;
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}
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}
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return OnlyAvailablePred;
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}
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/// getSingleUnscheduledSucc - If there is exactly one unscheduled successor
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/// of SU, return it, otherwise return null.
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static SUnit *getSingleUnscheduledSucc(SUnit *SU) {
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SUnit *OnlyAvailableSucc = 0;
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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SUnit &Succ = *I->getSUnit();
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if (!Succ.isScheduled) {
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// We found an available, but not scheduled, successor. If it's the
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// only one we have found, keep track of it... otherwise give up.
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if (OnlyAvailableSucc && OnlyAvailableSucc != &Succ)
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return 0;
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OnlyAvailableSucc = &Succ;
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}
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}
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return OnlyAvailableSucc;
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}
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// Constants used to denote relative importance of
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// heuristic components for cost computation.
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static const unsigned PriorityOne = 200;
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static const unsigned PriorityTwo = 100;
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static const unsigned PriorityThree = 50;
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static const unsigned PriorityFour = 20;
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static const unsigned ScaleTwo = 10;
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static const unsigned FactorOne = 2;
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@ -685,19 +739,44 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
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ResCount += PriorityOne;
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// Critical path first.
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if (Q.getID() == TopQID)
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if (Q.getID() == TopQID) {
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ResCount += (SU->getHeight() * ScaleTwo);
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else
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// If resources are available for it, multiply the
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// chance of scheduling.
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if (Top.ResourceModel->isResourceAvailable(SU))
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ResCount <<= FactorOne;
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} else {
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ResCount += (SU->getDepth() * ScaleTwo);
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// If resources are available for it, multiply the
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// chance of scheduling.
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if (DAG->getTopResourceModel()->isResourceAvailable(SU))
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ResCount <<= FactorOne;
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// If resources are available for it, multiply the
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// chance of scheduling.
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if (Bot.ResourceModel->isResourceAvailable(SU))
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ResCount <<= FactorOne;
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}
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unsigned NumNodesBlocking = 0;
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if (Q.getID() == TopQID) {
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// How many SUs does it block from scheduling?
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// Look at all of the successors of this node.
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// Count the number of nodes that
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// this node is the sole unscheduled node for.
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for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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if (getSingleUnscheduledPred(I->getSUnit()) == SU)
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++NumNodesBlocking;
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} else {
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// How many unscheduled predecessors block this node?
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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if (getSingleUnscheduledSucc(I->getSUnit()) == SU)
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++NumNodesBlocking;
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}
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ResCount += (NumNodesBlocking * ScaleTwo);
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// Factor in reg pressure as a heuristic.
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ResCount -= (Delta.Excess.UnitIncrease * PriorityThree);
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ResCount -= (Delta.CriticalMax.UnitIncrease * PriorityThree);
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ResCount -= (Delta.Excess.UnitIncrease*PriorityThree);
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ResCount -= (Delta.CriticalMax.UnitIncrease*PriorityThree);
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DEBUG(if (verbose) dbgs() << " Total(" << ResCount << ")");
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@ -736,7 +815,6 @@ pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker,
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continue;
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}
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// Best cost.
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if (CurrentCost > Candidate.SCost) {
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DEBUG(traceCandidate("CCAND", Q, *I));
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@ -859,14 +937,14 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
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}
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/// Update the scheduler's state after scheduling a node. This is the same node
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/// that was just returned by pickNode(). However, VLIWMachineScheduler needs to update
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/// it's state based on the current cycle before MachineSchedStrategy does.
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/// that was just returned by pickNode(). However, VLIWMachineScheduler needs
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/// to update it's state based on the current cycle before MachineSchedStrategy
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/// does.
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void ConvergingVLIWScheduler::schedNode(SUnit *SU, bool IsTopNode) {
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if (IsTopNode) {
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SU->TopReadyCycle = Top.CurrCycle;
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Top.bumpNode(SU);
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}
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else {
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} else {
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SU->BotReadyCycle = Bot.CurrCycle;
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Bot.bumpNode(SU);
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}
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@ -40,11 +40,10 @@ using namespace llvm;
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namespace llvm {
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class VLIWMachineScheduler;
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/// MachineSchedStrategy - Interface used by VLIWMachineScheduler to drive the selected
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/// scheduling algorithm.
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/// MachineSchedStrategy - Interface used by VLIWMachineScheduler to drive
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/// the selected scheduling algorithm.
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///
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/// If this works well and targets wish to reuse VLIWMachineScheduler, we may expose it
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/// in ScheduleDAGInstrs.h
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/// TODO: Move this to ScheduleDAGInstrs.h
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class MachineSchedStrategy {
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public:
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virtual ~MachineSchedStrategy() {}
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@ -57,7 +56,8 @@ public:
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/// be scheduled at the bottom.
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virtual SUnit *pickNode(bool &IsTopNode) = 0;
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/// Notify MachineSchedStrategy that VLIWMachineScheduler has scheduled a node.
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/// Notify MachineSchedStrategy that VLIWMachineScheduler has
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/// scheduled a node.
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virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
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/// When all predecessor dependencies have been resolved, free this node for
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@ -69,7 +69,8 @@ public:
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};
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//===----------------------------------------------------------------------===//
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// ConvergingVLIWScheduler - Implementation of the standard MachineSchedStrategy.
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// ConvergingVLIWScheduler - Implementation of the standard
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// MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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/// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
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@ -123,12 +124,197 @@ public:
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}
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};
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/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics to balance
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/// the schedule.
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class VLIWResourceModel {
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/// ResourcesModel - Represents VLIW state.
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/// Not limited to VLIW targets per say, but assumes
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/// definition of DFA by a target.
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DFAPacketizer *ResourcesModel;
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const InstrItineraryData *InstrItins;
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/// Local packet/bundle model. Purely
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/// internal to the MI schedulre at the time.
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std::vector<SUnit*> Packet;
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/// Total packets created.
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unsigned TotalPackets;
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public:
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VLIWResourceModel(MachineSchedContext *C, const InstrItineraryData *IID) :
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InstrItins(IID), TotalPackets(0) {
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const TargetMachine &TM = C->MF->getTarget();
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ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
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// This hard requirement could be relaxed,
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// but for now do not let it proceed.
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assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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Packet.resize(InstrItins->SchedModel->IssueWidth);
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Packet.clear();
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ResourcesModel->clearResources();
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}
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VLIWResourceModel(const TargetMachine &TM) :
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InstrItins(TM.getInstrItineraryData()), TotalPackets(0) {
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ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
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// This hard requirement could be relaxed,
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// but for now do not let it proceed.
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assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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Packet.resize(InstrItins->SchedModel->IssueWidth);
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Packet.clear();
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ResourcesModel->clearResources();
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}
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~VLIWResourceModel() {
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delete ResourcesModel;
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}
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void resetPacketState() {
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Packet.clear();
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}
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void resetDFA() {
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ResourcesModel->clearResources();
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}
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void reset() {
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Packet.clear();
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ResourcesModel->clearResources();
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}
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bool isResourceAvailable(SUnit *SU);
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bool reserveResources(SUnit *SU);
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unsigned getTotalPackets() const { return TotalPackets; }
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};
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class VLIWMachineScheduler : public ScheduleDAGInstrs {
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/// AA - AliasAnalysis for making memory reference queries.
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AliasAnalysis *AA;
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RegisterClassInfo *RegClassInfo;
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MachineSchedStrategy *SchedImpl;
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MachineBasicBlock::iterator LiveRegionEnd;
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/// Register pressure in this region computed by buildSchedGraph.
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IntervalPressure RegPressure;
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RegPressureTracker RPTracker;
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/// List of pressure sets that exceed the target's pressure limit before
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/// scheduling, listed in increasing set ID order. Each pressure set is paired
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/// with its max pressure in the currently scheduled regions.
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std::vector<PressureElement> RegionCriticalPSets;
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/// The top of the unscheduled zone.
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MachineBasicBlock::iterator CurrentTop;
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IntervalPressure TopPressure;
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RegPressureTracker TopRPTracker;
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/// The bottom of the unscheduled zone.
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MachineBasicBlock::iterator CurrentBottom;
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IntervalPressure BotPressure;
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RegPressureTracker BotRPTracker;
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#ifndef NDEBUG
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/// The number of instructions scheduled so far. Used to cut off the
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/// scheduler at the point determined by misched-cutoff.
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unsigned NumInstrsScheduled;
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#endif
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/// Total packets in the region.
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unsigned TotalPackets;
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||||
const MachineLoopInfo *MLI;
|
||||
public:
|
||||
VLIWMachineScheduler(MachineSchedContext *C, MachineSchedStrategy *S):
|
||||
ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
|
||||
AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
|
||||
RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
|
||||
CurrentBottom(), BotRPTracker(BotPressure), MLI(C->MLI) {
|
||||
#ifndef NDEBUG
|
||||
NumInstrsScheduled = 0;
|
||||
#endif
|
||||
TotalPackets = 0;
|
||||
}
|
||||
|
||||
virtual ~VLIWMachineScheduler() {
|
||||
delete SchedImpl;
|
||||
}
|
||||
|
||||
MachineBasicBlock::iterator top() const { return CurrentTop; }
|
||||
MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
|
||||
|
||||
/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
|
||||
/// region. This covers all instructions in a block, while schedule() may only
|
||||
/// cover a subset.
|
||||
void enterRegion(MachineBasicBlock *bb,
|
||||
MachineBasicBlock::iterator begin,
|
||||
MachineBasicBlock::iterator end,
|
||||
unsigned endcount);
|
||||
|
||||
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
|
||||
/// time to do some work.
|
||||
void schedule();
|
||||
|
||||
unsigned CurCycle;
|
||||
|
||||
/// Get current register pressure for the top scheduled instructions.
|
||||
const IntervalPressure &getTopPressure() const { return TopPressure; }
|
||||
const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
|
||||
|
||||
/// Get current register pressure for the bottom scheduled instructions.
|
||||
const IntervalPressure &getBotPressure() const { return BotPressure; }
|
||||
const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
|
||||
|
||||
/// Get register pressure for the entire scheduling region before scheduling.
|
||||
const IntervalPressure &getRegPressure() const { return RegPressure; }
|
||||
|
||||
const std::vector<PressureElement> &getRegionCriticalPSets() const {
|
||||
return RegionCriticalPSets;
|
||||
}
|
||||
|
||||
/// getIssueWidth - Return the max instructions per scheduling group.
|
||||
unsigned getIssueWidth() const {
|
||||
return (InstrItins && InstrItins->SchedModel)
|
||||
? InstrItins->SchedModel->IssueWidth : 1;
|
||||
}
|
||||
|
||||
/// getNumMicroOps - Return the number of issue slots required for this MI.
|
||||
unsigned getNumMicroOps(MachineInstr *MI) const {
|
||||
return 1;
|
||||
//if (!InstrItins) return 1;
|
||||
//int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
|
||||
//return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
|
||||
}
|
||||
|
||||
private:
|
||||
void scheduleNodeTopDown(SUnit *SU);
|
||||
void listScheduleTopDown();
|
||||
|
||||
void initRegPressure();
|
||||
void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
|
||||
|
||||
void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
|
||||
bool checkSchedLimit();
|
||||
|
||||
void releaseRoots();
|
||||
|
||||
void releaseSucc(SUnit *SU, SDep *SuccEdge);
|
||||
void releaseSuccessors(SUnit *SU);
|
||||
void releasePred(SUnit *SU, SDep *PredEdge);
|
||||
void releasePredecessors(SUnit *SU);
|
||||
|
||||
void placeDebugValues();
|
||||
};
|
||||
|
||||
/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
|
||||
/// to balance the schedule.
|
||||
class ConvergingVLIWScheduler : public MachineSchedStrategy {
|
||||
|
||||
/// Store the state used by ConvergingVLIWScheduler heuristics, required for the
|
||||
/// lifetime of one invocation of pickNode().
|
||||
/// Store the state used by ConvergingVLIWScheduler heuristics, required
|
||||
/// for the lifetime of one invocation of pickNode().
|
||||
struct SchedCandidate {
|
||||
// The best SUnit candidate.
|
||||
SUnit *SU;
|
||||
|
|
@ -157,6 +343,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
|
|||
bool CheckPending;
|
||||
|
||||
ScheduleHazardRecognizer *HazardRec;
|
||||
VLIWResourceModel *ResourceModel;
|
||||
|
||||
unsigned CurrCycle;
|
||||
unsigned IssueCount;
|
||||
|
|
@ -172,10 +359,14 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
|
|||
SchedBoundary(unsigned ID, const Twine &Name):
|
||||
DAG(0), Available(ID, Name+".A"),
|
||||
Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
|
||||
CheckPending(false), HazardRec(0), CurrCycle(0), IssueCount(0),
|
||||
CheckPending(false), HazardRec(0), ResourceModel(0),
|
||||
CurrCycle(0), IssueCount(0),
|
||||
MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
|
||||
|
||||
~SchedBoundary() { delete HazardRec; }
|
||||
~SchedBoundary() {
|
||||
delete ResourceModel;
|
||||
delete HazardRec;
|
||||
}
|
||||
|
||||
bool isTop() const {
|
||||
return Available.getID() == ConvergingVLIWScheduler::TopQID;
|
||||
|
|
@ -240,183 +431,6 @@ protected:
|
|||
#endif
|
||||
};
|
||||
|
||||
class VLIWResourceModel {
|
||||
/// ResourcesModel - Represents VLIW state.
|
||||
/// Not limited to VLIW targets per say, but assumes
|
||||
/// definition of DFA by a target.
|
||||
DFAPacketizer *ResourcesModel;
|
||||
|
||||
const InstrItineraryData *InstrItins;
|
||||
|
||||
/// Local packet/bundle model. Purely
|
||||
/// internal to the MI schedulre at the time.
|
||||
std::vector<SUnit*> Packet;
|
||||
|
||||
/// Total packets created.
|
||||
unsigned TotalPackets;
|
||||
|
||||
public:
|
||||
VLIWResourceModel(MachineSchedContext *C, const InstrItineraryData *IID) :
|
||||
InstrItins(IID), TotalPackets(0) {
|
||||
const TargetMachine &TM = C->MF->getTarget();
|
||||
ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
|
||||
|
||||
// This hard requirement could be relaxed, but for now do not let it proceed.
|
||||
assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
|
||||
|
||||
Packet.resize(InstrItins->SchedModel->IssueWidth);
|
||||
Packet.clear();
|
||||
ResourcesModel->clearResources();
|
||||
}
|
||||
|
||||
~VLIWResourceModel() {
|
||||
delete ResourcesModel;
|
||||
}
|
||||
|
||||
void resetPacketState() {
|
||||
Packet.clear();
|
||||
}
|
||||
|
||||
void resetDFA() {
|
||||
ResourcesModel->clearResources();
|
||||
}
|
||||
|
||||
bool isResourceAvailable(SUnit *SU);
|
||||
void reserveResources(SUnit *SU);
|
||||
unsigned getTotalPackets() const { return TotalPackets; }
|
||||
};
|
||||
|
||||
class VLIWMachineScheduler : public ScheduleDAGInstrs {
|
||||
/// AA - AliasAnalysis for making memory reference queries.
|
||||
AliasAnalysis *AA;
|
||||
|
||||
RegisterClassInfo *RegClassInfo;
|
||||
MachineSchedStrategy *SchedImpl;
|
||||
|
||||
/// state separatly for top/bottom sectioins.
|
||||
VLIWResourceModel *TopResourceModel;
|
||||
VLIWResourceModel *BotResourceModel;
|
||||
|
||||
MachineBasicBlock::iterator LiveRegionEnd;
|
||||
|
||||
/// Register pressure in this region computed by buildSchedGraph.
|
||||
IntervalPressure RegPressure;
|
||||
RegPressureTracker RPTracker;
|
||||
|
||||
/// List of pressure sets that exceed the target's pressure limit before
|
||||
/// scheduling, listed in increasing set ID order. Each pressure set is paired
|
||||
/// with its max pressure in the currently scheduled regions.
|
||||
std::vector<PressureElement> RegionCriticalPSets;
|
||||
|
||||
/// The top of the unscheduled zone.
|
||||
MachineBasicBlock::iterator CurrentTop;
|
||||
IntervalPressure TopPressure;
|
||||
RegPressureTracker TopRPTracker;
|
||||
|
||||
/// The bottom of the unscheduled zone.
|
||||
MachineBasicBlock::iterator CurrentBottom;
|
||||
IntervalPressure BotPressure;
|
||||
RegPressureTracker BotRPTracker;
|
||||
|
||||
#ifndef NDEBUG
|
||||
/// The number of instructions scheduled so far. Used to cut off the
|
||||
/// scheduler at the point determined by misched-cutoff.
|
||||
unsigned NumInstrsScheduled;
|
||||
#endif
|
||||
|
||||
/// Total packets in the region.
|
||||
unsigned TotalPackets;
|
||||
|
||||
const MachineLoopInfo *MLI;
|
||||
public:
|
||||
VLIWMachineScheduler(MachineSchedContext *C, MachineSchedStrategy *S):
|
||||
ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
|
||||
AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
|
||||
RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
|
||||
CurrentBottom(), BotRPTracker(BotPressure), MLI(C->MLI) {
|
||||
|
||||
TopResourceModel = new VLIWResourceModel(C, InstrItins);
|
||||
BotResourceModel = new VLIWResourceModel(C, InstrItins);
|
||||
|
||||
#ifndef NDEBUG
|
||||
NumInstrsScheduled = 0;
|
||||
#endif
|
||||
TotalPackets = 0;
|
||||
}
|
||||
|
||||
virtual ~VLIWMachineScheduler() {
|
||||
delete SchedImpl;
|
||||
delete TopResourceModel;
|
||||
delete BotResourceModel;
|
||||
}
|
||||
|
||||
MachineBasicBlock::iterator top() const { return CurrentTop; }
|
||||
MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
|
||||
|
||||
/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
|
||||
/// region. This covers all instructions in a block, while schedule() may only
|
||||
/// cover a subset.
|
||||
void enterRegion(MachineBasicBlock *bb,
|
||||
MachineBasicBlock::iterator begin,
|
||||
MachineBasicBlock::iterator end,
|
||||
unsigned endcount);
|
||||
|
||||
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
|
||||
/// time to do some work.
|
||||
void schedule();
|
||||
|
||||
unsigned CurCycle;
|
||||
|
||||
/// Get current register pressure for the top scheduled instructions.
|
||||
const IntervalPressure &getTopPressure() const { return TopPressure; }
|
||||
const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
|
||||
|
||||
/// Get current register pressure for the bottom scheduled instructions.
|
||||
const IntervalPressure &getBotPressure() const { return BotPressure; }
|
||||
const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
|
||||
|
||||
/// Get register pressure for the entire scheduling region before scheduling.
|
||||
const IntervalPressure &getRegPressure() const { return RegPressure; }
|
||||
|
||||
const std::vector<PressureElement> &getRegionCriticalPSets() const {
|
||||
return RegionCriticalPSets;
|
||||
}
|
||||
|
||||
VLIWResourceModel *getTopResourceModel() { return TopResourceModel; }
|
||||
VLIWResourceModel *getBotResourceModel() { return BotResourceModel; }
|
||||
|
||||
/// getIssueWidth - Return the max instructions per scheduling group.
|
||||
unsigned getIssueWidth() const {
|
||||
return (InstrItins && InstrItins->SchedModel)
|
||||
? InstrItins->SchedModel->IssueWidth : 1;
|
||||
}
|
||||
|
||||
/// getNumMicroOps - Return the number of issue slots required for this MI.
|
||||
unsigned getNumMicroOps(MachineInstr *MI) const {
|
||||
if (!InstrItins) return 1;
|
||||
int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
|
||||
return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
|
||||
}
|
||||
|
||||
private:
|
||||
void scheduleNodeTopDown(SUnit *SU);
|
||||
void listScheduleTopDown();
|
||||
|
||||
void initRegPressure();
|
||||
void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
|
||||
|
||||
void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
|
||||
bool checkSchedLimit();
|
||||
|
||||
void releaseRoots();
|
||||
|
||||
void releaseSucc(SUnit *SU, SDep *SuccEdge);
|
||||
void releaseSuccessors(SUnit *SU);
|
||||
void releasePred(SUnit *SU, SDep *PredEdge);
|
||||
void releasePredecessors(SUnit *SU);
|
||||
|
||||
void placeDebugValues();
|
||||
};
|
||||
} // namespace
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue