forked from OSchip/llvm-project
Add test showing the update of access functions with in-scop defined base ptrs
This feature is currently not supported and an explicit assert to prevent the introduction of such accesses has been added in r282893. This test case allows to reproduce the assert (and without the assert the miscompile) added in r282893. It will help when adding such support at some point. llvm-svn: 292147
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; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-dir=%S \
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; RUN: -polly-codegen -analyze 2 >&1 < %s | FileCheck %s
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; XFAIL: *
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; Setting new access functions where the base pointer of the array that is newly
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; accessed is only loaded within the scop itself caused incorrect code to be
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; generated when invariant load hoisting is disabled. Since r282893 we assert
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; in such situations. This test case was added to demonstrate what needs to be
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; resolved to support such access functions.
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define void @invariant_base_ptr(float* noalias %Array, float** noalias %X,
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float* noalias %C) {
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start:
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br label %loop
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loop:
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%indvar = phi i64 [0, %start], [%indvar.next, %latch]
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%indvar.next = add i64 %indvar, 1
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%cmp = icmp slt i64 %indvar, 1024
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br i1 %cmp, label %body, label %exit
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body:
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%gep= getelementptr float, float* %Array, i64 %indvar
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store float 42.0, float* %gep
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br label %body2
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body2:
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%Base = load float*, float** %X
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%gep2 = getelementptr float, float* %Base, i64 %indvar
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%val2 = load float, float* %gep2
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store float %val2, float* %C
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br label %latch
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latch:
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br label %loop
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exit:
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ret void
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}
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@ -0,0 +1,54 @@
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{
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"arrays" : [
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{
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"name" : "MemRef_Array",
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"sizes" : [ "*" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_X",
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"sizes" : [ "*" ],
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"type" : "float*"
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},
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{
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"name" : "MemRef_Base",
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"sizes" : [ "*" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_C",
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"sizes" : [ "*" ],
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"type" : "float"
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}
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],
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"context" : "{ : }",
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"name" : "%loop---%exit",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_body[i0] -> MemRef_Base[i0] }"
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}
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],
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"domain" : "{ Stmt_body[i0] : 0 <= i0 <= 1023 }",
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"name" : "Stmt_body",
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"schedule" : "{ Stmt_body[i0] -> [i0, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_body2[i0] -> MemRef_Base[i0] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_body2[i0] -> MemRef_C[0] }"
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}
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],
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"domain" : "{ Stmt_body2[i0] : 0 <= i0 <= 1023 }",
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"name" : "Stmt_body2",
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"schedule" : "{ Stmt_body2[i0] -> [i0, 1] }"
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}
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]
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}
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