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SDAG: Implement Select instead of SelectImpl in MipsDAGToDAGISel 

- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

llvm-svn: 269519
This commit is contained in:
Justin Bogner 2016-05-13 23:55:59 +00:00
parent a4fcd3681f
commit eeae751429
6 changed files with 54 additions and 62 deletions
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16
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
View File

@ -241,7 +241,7 @@ bool Mips16DAGToDAGISel::selectAddr16(
/// Select instructions not customized! Used for /// Select instructions not customized! Used for
/// expanded, promoted and normal instructions /// expanded, promoted and normal instructions
std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) { bool Mips16DAGToDAGISel::trySelect(SDNode *Node) {
unsigned Opcode = Node->getOpcode(); unsigned Opcode = Node->getOpcode();
SDLoc DL(Node); SDLoc DL(Node);
@ -285,9 +285,8 @@ std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT, SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
SDValue(Carry,0), RHS); SDValue(Carry,0), RHS);
SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0));
SDValue(AddCarry,0)); return true;
return std::make_pair(true, Result);
} }
/// Mul with two results /// Mul with two results
@ -303,18 +302,19 @@ std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
CurDAG->RemoveDeadNode(Node); CurDAG->RemoveDeadNode(Node);
return std::make_pair(true, nullptr); return true;
} }
case ISD::MULHS: case ISD::MULHS:
case ISD::MULHU: { case ISD::MULHU: {
MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second; auto LoHi = selectMULT(Node, MultOpc, DL, NodeTy, false, true);
return std::make_pair(true, Result); ReplaceNode(Node, LoHi.second);
return true;
} }
} }
return std::make_pair(false, nullptr); return false;
} }
FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) { FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {

2
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
View File

@ -35,7 +35,7 @@ private:
bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base, bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Alias) override; SDValue &Offset, SDValue &Alias) override;
std::pair<bool, SDNode*> selectNode(SDNode *Node) override; bool trySelect(SDNode *Node) override;
void processFunctionAfterISel(MachineFunction &MF) override; void processFunctionAfterISel(MachineFunction &MF) override;

23
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -182,7 +182,7 @@ bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
/// Select instructions not customized! Used for /// Select instructions not customized! Used for
/// expanded, promoted and normal instructions /// expanded, promoted and normal instructions
SDNode *MipsDAGToDAGISel::SelectImpl(SDNode *Node) { void MipsDAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode = Node->getOpcode(); unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected // Dump information about the Node being selected
@ -192,21 +192,20 @@ SDNode *MipsDAGToDAGISel::SelectImpl(SDNode *Node) {
if (Node->isMachineOpcode()) { if (Node->isMachineOpcode()) {
DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
Node->setNodeId(-1); Node->setNodeId(-1);
return nullptr; return;
} }
// See if subclasses can handle this node. // See if subclasses can handle this node.
std::pair<bool, SDNode*> Ret = selectNode(Node); if (trySelect(Node))
return;
if (Ret.first)
return Ret.second;
switch(Opcode) { switch(Opcode) {
default: break; default: break;
// Get target GOT address. // Get target GOT address.
case ISD::GLOBAL_OFFSET_TABLE: case ISD::GLOBAL_OFFSET_TABLE:
return getGlobalBaseReg(); ReplaceNode(Node, getGlobalBaseReg());
return;
#ifndef NDEBUG #ifndef NDEBUG
case ISD::LOAD: case ISD::LOAD:
@ -220,15 +219,7 @@ SDNode *MipsDAGToDAGISel::SelectImpl(SDNode *Node) {
} }
// Select the default instruction // Select the default instruction
SDNode *ResNode = SelectCode(Node); SelectCode(Node);
DEBUG(errs() << "=> ");
if (ResNode == nullptr || ResNode == Node)
DEBUG(Node->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DEBUG(errs() << "\n");
return ResNode;
} }
bool MipsDAGToDAGISel:: bool MipsDAGToDAGISel::

4
llvm/lib/Target/Mips/MipsISelDAGToDAG.h
View File

@ -114,9 +114,9 @@ private:
/// starting at bit zero. /// starting at bit zero.
virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const; virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
SDNode *SelectImpl(SDNode *N) override; void Select(SDNode *N) override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0; virtual bool trySelect(SDNode *Node) = 0;
// getImm - Return a target constant with the specified value. // getImm - Return a target constant with the specified value.
inline SDValue getImm(const SDNode *Node, uint64_t Imm) { inline SDValue getImm(const SDNode *Node, uint64_t Imm) {

65
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -236,7 +236,7 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
} }
} }
SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, void MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
SDValue CmpLHS, SDLoc DL, SDValue CmpLHS, SDLoc DL,
SDNode *Node) const { SDNode *Node) const {
unsigned Opc = InFlag.getOpcode(); (void)Opc; unsigned Opc = InFlag.getOpcode(); (void)Opc;
@ -275,8 +275,7 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
if (!C || C->getZExtValue()) if (!C || C->getZExtValue())
AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS); AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0));
SDValue(AddCarry, 0));
} }
/// Match frameindex /// Match frameindex
@ -706,7 +705,7 @@ bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
return false; return false;
} }
std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
unsigned Opcode = Node->getOpcode(); unsigned Opcode = Node->getOpcode();
SDLoc DL(Node); SDLoc DL(Node);
@ -714,16 +713,14 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
// Instruction Selection not handled by the auto-generated // Instruction Selection not handled by the auto-generated
// tablegen selection should be handled here. // tablegen selection should be handled here.
/// ///
SDNode *Result;
switch(Opcode) { switch(Opcode) {
default: break; default: break;
case ISD::SUBE: { case ISD::SUBE: {
SDValue InFlag = Node->getOperand(2); SDValue InFlag = Node->getOperand(2);
unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu; unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node); selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
return std::make_pair(true, Result); return true;
} }
case ISD::ADDE: { case ISD::ADDE: {
@ -731,8 +728,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
break; break;
SDValue InFlag = Node->getOperand(2); SDValue InFlag = Node->getOperand(2);
unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu; unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node); selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
return std::make_pair(true, Result); return true;
} }
case ISD::ConstantFP: { case ISD::ConstantFP: {
@ -741,20 +738,20 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
if (Subtarget->isGP64bit()) { if (Subtarget->isGP64bit()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
Mips::ZERO_64, MVT::i64); Mips::ZERO_64, MVT::i64);
Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero); ReplaceNode(Node,
CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
} else if (Subtarget->isFP64bit()) { } else if (Subtarget->isFP64bit()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
Mips::ZERO, MVT::i32); Mips::ZERO, MVT::i32);
Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64, ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
Zero, Zero); MVT::f64, Zero, Zero));
} else { } else {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
Mips::ZERO, MVT::i32); Mips::ZERO, MVT::i32);
Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero, ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
Zero); MVT::f64, Zero, Zero));
} }
return true;
return std::make_pair(true, Result);
} }
break; break;
} }
@ -797,7 +794,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
SDValue(RegOpnd, 0), ImmOpnd); SDValue(RegOpnd, 0), ImmOpnd);
} }
return std::make_pair(true, RegOpnd); ReplaceNode(Node, RegOpnd);
return true;
} }
case ISD::INTRINSIC_W_CHAIN: { case ISD::INTRINSIC_W_CHAIN: {
@ -810,7 +808,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
SDValue RegIdx = Node->getOperand(2); SDValue RegIdx = Node->getOperand(2);
SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL, SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
getMSACtrlReg(RegIdx), MVT::i32); getMSACtrlReg(RegIdx), MVT::i32);
return std::make_pair(true, Reg.getNode()); ReplaceNode(Node, Reg.getNode());
return true;
} }
} }
break; break;
@ -824,10 +823,10 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
case Intrinsic::mips_move_v: case Intrinsic::mips_move_v:
// Like an assignment but will always produce a move.v even if // Like an assignment but will always produce a move.v even if
// unnecessary. // unnecessary.
return std::make_pair(true, ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
CurDAG->getMachineNode(Mips::MOVE_V, DL, Node->getValueType(0),
Node->getValueType(0), Node->getOperand(1)));
Node->getOperand(1))); return true;
} }
break; break;
} }
@ -843,7 +842,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
SDValue Value = Node->getOperand(3); SDValue Value = Node->getOperand(3);
SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL, SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
getMSACtrlReg(RegIdx), Value); getMSACtrlReg(RegIdx), Value);
return std::make_pair(true, ChainOut.getNode()); ReplaceNode(Node, ChainOut.getNode());
return true;
} }
} }
break; break;
@ -868,8 +868,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
SDValue(Rdhwr, 0)); SDValue(Rdhwr, 0));
SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT); SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
ReplaceUses(SDValue(Node, 0), ResNode); ReplaceNode(Node, ResNode.getNode());
return std::make_pair(true, ResNode.getNode()); return true;
} }
case ISD::BUILD_VECTOR: { case ISD::BUILD_VECTOR: {
@ -894,16 +894,16 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
EVT ViaVecTy; EVT ViaVecTy;
if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector()) if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
return std::make_pair(false, nullptr); return false;
if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
HasAnyUndefs, 8, HasAnyUndefs, 8,
!Subtarget->isLittle())) !Subtarget->isLittle()))
return std::make_pair(false, nullptr); return false;
switch (SplatBitSize) { switch (SplatBitSize) {
default: default:
return std::make_pair(false, nullptr); return false;
case 8: case 8:
LdiOp = Mips::LDI_B; LdiOp = Mips::LDI_B;
ViaVecTy = MVT::v16i8; ViaVecTy = MVT::v16i8;
@ -923,7 +923,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
} }
if (!SplatValue.isSignedIntN(10)) if (!SplatValue.isSignedIntN(10))
return std::make_pair(false, nullptr); return false;
SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL, SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
ViaVecTy.getVectorElementType()); ViaVecTy.getVectorElementType());
@ -944,12 +944,13 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
MVT::i32)); MVT::i32));
} }
return std::make_pair(true, Res); ReplaceNode(Node, Res);
return true;
} }
} }
return std::make_pair(false, nullptr); return false;
} }
bool MipsSEDAGToDAGISel:: bool MipsSEDAGToDAGISel::

6
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
View File

@ -37,8 +37,8 @@ private:
std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc dl, std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc dl,
EVT Ty, bool HasLo, bool HasHi); EVT Ty, bool HasLo, bool HasHi);
SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS, void selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS, SDLoc DL,
SDLoc DL, SDNode *Node) const; SDNode *Node) const;
bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const; bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset, bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
@ -111,7 +111,7 @@ private:
/// starting at bit zero. /// starting at bit zero.
bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override; bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override;
std::pair<bool, SDNode*> selectNode(SDNode *Node) override; bool trySelect(SDNode *Node) override;
void processFunctionAfterISel(MachineFunction &MF) override; void processFunctionAfterISel(MachineFunction &MF) override;