forked from OSchip/llvm-project
[InstSimplify] tests for D48828: fold extraction from std::pair
This commit includes unit tests for D48828, which enhances InstSimplify to enable jump threading with a method whose return type is std::pair<int, bool> or std::pair<bool, int>. I am going to commit the actual transformation later. llvm-svn: 338107
This commit is contained in:
Hiroshi Inoue
parent
03948d0e0f
commit
eeab694cea
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@ -964,3 +964,148 @@ define i32 @reversed_not(i32 %a) {
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%or = or i32 %a, %nega
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ret i32 %or
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}
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define i64 @shl_or_and1(i32 %a, i1 %b) {
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; CHECK-LABEL: @shl_or_and1(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1
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; CHECK-NEXT: ret i64 [[TMP5]]
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;
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i1 %b to i64
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%tmp3 = shl nuw i64 %tmp1, 32
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = and i64 %tmp4, 1
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ret i64 %tmp5
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}
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define i64 @shl_or_and2(i32 %a, i1 %b) {
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; CHECK-LABEL: @shl_or_and2(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967296
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; CHECK-NEXT: ret i64 [[TMP5]]
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;
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%tmp1 = zext i1 %b to i64
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%tmp2 = zext i32 %a to i64
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%tmp3 = shl nuw i64 %tmp1, 32
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = and i64 %tmp4, 4294967296
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ret i64 %tmp5
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}
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define i32 @shl_or_and3(i32 %a, i32 %b) {
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; concatinate two 32-bit integers and extract lower 32-bit
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; CHECK-LABEL: @shl_or_and3(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
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; CHECK-NEXT: ret i32 [[TMP6]]
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;
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = shl nuw i64 %tmp1, 32
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = and i64 %tmp4, 4294967295
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%tmp6 = trunc i64 %tmp5 to i32
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ret i32 %tmp6
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}
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define i32 @shl_or_and4(i16 %a, i16 %b) {
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; concatinate two 16-bit integers and extract higher 16-bit
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; CHECK-LABEL: @shl_or_and4(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65536
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; CHECK-NEXT: ret i32 [[TMP5]]
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;
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%tmp1 = zext i16 %a to i32
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%tmp2 = zext i16 %b to i32
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%tmp3 = shl nuw i32 %tmp1, 16
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = and i32 %tmp4, 4294901760 ; mask with 0xFFFF0000
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ret i32 %tmp5
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}
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define i64 @shl_or_and5(i64 %a, i1 %b) {
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; CHECK-LABEL: @shl_or_and5(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i64 [[A:%.*]] to i128
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; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i128 [[TMP1]], 64
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; CHECK-NEXT: [[TMP4:%.*]] = or i128 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i128 [[TMP4]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64
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; CHECK-NEXT: ret i64 [[TMP6]]
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;
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%tmp1 = zext i64 %a to i128
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%tmp2 = zext i1 %b to i128
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%tmp3 = shl nuw i128 %tmp1, 64
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%tmp4 = or i128 %tmp2, %tmp3
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%tmp5 = and i128 %tmp4, 1
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%tmp6 = trunc i128 %tmp5 to i64
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ret i64 %tmp6
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}
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define i32 @shl_or_and6(i16 %a, i16 %b) {
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; A variation of above test case, but fails due to the mask value
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; CHECK-LABEL: @shl_or_and6(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65535
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; CHECK-NEXT: ret i32 [[TMP5]]
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;
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%tmp1 = zext i16 %a to i32
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%tmp2 = zext i16 %b to i32
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%tmp3 = shl nuw i32 %tmp1, 16
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = and i32 %tmp4, 4294901761 ; mask with 0xFFFF0001
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ret i32 %tmp5
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}
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define i32 @shl_or_and7(i16 %a, i16 %b) {
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; A variation of above test case, but fails due to the mask value
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; CHECK-LABEL: @shl_or_and7(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -131072
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; CHECK-NEXT: ret i32 [[TMP5]]
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;
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%tmp1 = zext i16 %a to i32
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%tmp2 = zext i16 %b to i32
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%tmp3 = shl nuw i32 %tmp1, 16
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = and i32 %tmp4, 4294836224 ; mask with 0xFFFE0000
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ret i32 %tmp5
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}
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define i32 @shl_or_and8(i16 %a, i16 %b) {
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; A variation of above test case, but fails due to the mask value
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; CHECK-LABEL: @shl_or_and8(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 131071
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; CHECK-NEXT: ret i32 [[TMP5]]
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;
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%tmp1 = zext i16 %a to i32
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%tmp2 = zext i16 %b to i32
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%tmp3 = shl nuw i32 %tmp1, 16
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF
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ret i32 %tmp5
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}
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@ -175,3 +175,41 @@ define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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ret <2 x i8> %r
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}
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define i32 @shl_or_shr(i32 %a, i32 %b) {
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; CHECK-LABEL: @shl_or_shr(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 32
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
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; CHECK-NEXT: ret i32 [[TMP6]]
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;
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = shl nuw i64 %tmp1, 32
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = lshr i64 %tmp4, 32
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%tmp6 = trunc i64 %tmp5 to i32
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ret i32 %tmp6
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}
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define i32 @shl_or_shr2(i32 %a, i32 %b) {
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; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated.
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; CHECK-LABEL: @shl_or_shr2(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31
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; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
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; CHECK-NEXT: ret i32 [[TMP6]]
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;
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = shl nuw i64 %tmp1, 31
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = lshr i64 %tmp4, 31
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%tmp6 = trunc i64 %tmp5 to i32
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ret i32 %tmp6
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}
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@ -0,0 +1,122 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -newgvn -S | FileCheck %s
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; RUN: opt < %s -newgvn -jump-threading -S | FileCheck --check-prefix=CHECK-JT %s
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; This test is expected to fail until the transformation is committed.
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; XFAIL: *
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define signext i32 @testBI(i32 signext %v) {
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; Test with std::pair<bool, int>
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; based on the following C++ code
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; std::pair<bool, int> callee(int v) {
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; int a = dummy(v);
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; if (a) return std::make_pair(true, dummy(a));
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; else return std::make_pair(v < 0, v);
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; }
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; int func(int v) {
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; std::pair<bool, int> rc = callee(v);
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; if (rc.first) dummy(0);
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; return rc.second;
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; }
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; CHECK-LABEL: @testBI(
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; CHECK: _ZL6calleei.exit:
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; CHECK: [[PHIOFOPS:%.*]] = phi i64 [ 1, %if.then.i ], [ {{%.*}}, %if.else.i ]
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; CHECK: [[TOBOOL:%.*]] = icmp eq i64 [[PHIOFOPS]], 0
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;
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; CHECK-JT-LABEL: @testBI(
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; CHECK-JT: _ZL6calleei.exit.thread:
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;
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entry:
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%call.i = call signext i32 @dummy(i32 signext %v)
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%tobool.i = icmp eq i32 %call.i, 0
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br i1 %tobool.i, label %if.else.i, label %if.then.i
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if.then.i: ; preds = %entry
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%call2.i = call signext i32 @dummy(i32 signext %call.i)
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%retval.sroa.22.0.insert.ext.i.i = zext i32 %call2.i to i64
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%retval.sroa.22.0.insert.shift.i.i = shl nuw i64 %retval.sroa.22.0.insert.ext.i.i, 32
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%retval.sroa.0.0.insert.insert.i.i = or i64 %retval.sroa.22.0.insert.shift.i.i, 1
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br label %_ZL6calleei.exit
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if.else.i: ; preds = %entry
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%.lobit.i = lshr i32 %v, 31
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%0 = zext i32 %.lobit.i to i64
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%retval.sroa.22.0.insert.ext.i8.i = zext i32 %v to i64
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%retval.sroa.22.0.insert.shift.i9.i = shl nuw i64 %retval.sroa.22.0.insert.ext.i8.i, 32
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%retval.sroa.0.0.insert.insert.i11.i = or i64 %retval.sroa.22.0.insert.shift.i9.i, %0
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br label %_ZL6calleei.exit
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_ZL6calleei.exit: ; preds = %if.then.i, %if.else.i
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%retval.sroa.0.0.i = phi i64 [ %retval.sroa.0.0.insert.insert.i.i, %if.then.i ], [ %retval.sroa.0.0.insert.insert.i11.i, %if.else.i ]
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%rc.sroa.43.0.extract.shift = lshr i64 %retval.sroa.0.0.i, 32
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%rc.sroa.43.0.extract.trunc = trunc i64 %rc.sroa.43.0.extract.shift to i32
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%1 = and i64 %retval.sroa.0.0.i, 1
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%tobool = icmp eq i64 %1, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %_ZL6calleei.exit
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%call1 = call signext i32 @dummy(i32 signext 0)
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br label %if.end
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if.end: ; preds = %_ZL6calleei.exit, %if.then
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ret i32 %rc.sroa.43.0.extract.trunc
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}
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define signext i32 @testIB(i32 signext %v) {
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; Test with std::pair<int, bool>
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; based on the following C++ code
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; std::pair<int, bool> callee(int v) {
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; int a = dummy(v);
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; if (a) return std::make_pair(dummy(v), true);
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; else return std::make_pair(v, v < 0);
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; }
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; int func(int v) {
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; std::pair<int, bool> rc = callee(v);
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; if (rc.second) dummy(0);
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; return rc.first;
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; }
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; CHECK-LABEL: @testIB(
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; CHECK: _ZL6calleei.exit:
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; CHECK: [[PHIOFOPS:%.*]] = phi i64 [ 4294967296, %if.then.i ], [ {{%.*}}, %if.else.i ]
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; CHECK: [[TOBOOL:%.*]] = icmp eq i64 [[PHIOFOPS]], 0
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;
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; CHECK-JT-LABEL: @testIB(
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; CHECK-JT: _ZL6calleei.exit.thread:
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;
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entry:
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%call.i = call signext i32 @dummy(i32 signext %v)
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%tobool.i = icmp eq i32 %call.i, 0
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br i1 %tobool.i, label %if.else.i, label %if.then.i
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if.then.i: ; preds = %entry
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%call1.i = call signext i32 @dummy(i32 signext %v)
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%retval.sroa.0.0.insert.ext.i.i = zext i32 %call1.i to i64
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%retval.sroa.0.0.insert.insert.i.i = or i64 %retval.sroa.0.0.insert.ext.i.i, 4294967296
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br label %_ZL6calleei.exit
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if.else.i: ; preds = %entry
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%.lobit.i = lshr i32 %v, 31
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%0 = zext i32 %.lobit.i to i64
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%retval.sroa.2.0.insert.shift.i8.i = shl nuw nsw i64 %0, 32
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%retval.sroa.0.0.insert.ext.i9.i = zext i32 %v to i64
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%retval.sroa.0.0.insert.insert.i10.i = or i64 %retval.sroa.2.0.insert.shift.i8.i, %retval.sroa.0.0.insert.ext.i9.i
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br label %_ZL6calleei.exit
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_ZL6calleei.exit: ; preds = %if.then.i, %if.else.i
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%retval.sroa.0.0.i = phi i64 [ %retval.sroa.0.0.insert.insert.i.i, %if.then.i ], [ %retval.sroa.0.0.insert.insert.i10.i, %if.else.i ]
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%rc.sroa.0.0.extract.trunc = trunc i64 %retval.sroa.0.0.i to i32
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%1 = and i64 %retval.sroa.0.0.i, 4294967296
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%tobool = icmp eq i64 %1, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %_ZL6calleei.exit
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%call1 = call signext i32 @dummy(i32 signext 0)
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br label %if.end
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if.end: ; preds = %_ZL6calleei.exit, %if.then
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ret i32 %rc.sroa.0.0.extract.trunc
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}
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declare signext i32 @dummy(i32 signext %v)
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