From ee7c5659d77c0eeb2e74101b0f884f25516d19f5 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Mon, 29 Nov 2010 22:37:46 +0000
Subject: [PATCH] Thumb encodings for conditional moves.

llvm-svn: 120334
---
 llvm/lib/Target/ARM/ARMInstrThumb.td | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 5ac8b98832a8..5dae5bd7a9b7 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1210,12 +1210,24 @@ let usesCustomInserter = 1 in  // Expanded after instruction selection.
 let neverHasSideEffects = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
-              T1Special<{1,0,?,?}>;
+              T1Special<{1,0,?,?}> {
+  bits<4> rhs;
+  bits<4> dst;
+  let Inst{7}   = dst{3};
+  let Inst{6-3} = rhs;
+  let Inst{2-0} = dst{2-0};
+}
 
 let isMoveImm = 1 in
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
-              T1General<{1,0,0,?,?}>;
+              T1General<{1,0,0,?,?}> {
+  bits<8> rhs;
+  bits<3> dst;
+  let Inst{10-8} = dst;
+  let Inst{7-0}  = rhs;
+}
+
 } // neverHasSideEffects
 
 // tLEApcrel - Load a pc-relative address into a register without offending the