forked from OSchip/llvm-project
[AArch64] Cost-model i8 vector loads/stores
Loads of <4 x i8> vectors were modeled as extremely expensive. And while we don't have a load instruction that supports this, it isn't that expensive to create a vector of i8 elements. The codegen for this was fixed/optimised in D105110. This now tweaks the cost model and enables SLP vectorisation of my motivating case loadi8.ll. Differential Revision: https://reviews.llvm.org/D103629
This commit is contained in:
Sjoerd Meijer
parent
a96911c49b
commit
ee752134ac
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@ -1423,8 +1423,9 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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const Instruction *I) {
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EVT VT = TLI->getValueType(DL, Ty, true);
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// Type legalization can't handle structs
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if (TLI->getValueType(DL, Ty, true) == MVT::Other)
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if (VT == MVT::Other)
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return BaseT::getMemoryOpCost(Opcode, Ty, Alignment, AddressSpace,
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CostKind);
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@ -1451,23 +1452,14 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
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return LT.first * 2 * AmortizationCost;
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}
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// Check truncating stores and extending loads.
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if (useNeonVector(Ty) &&
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cast<VectorType>(Ty)->getElementType()->isIntegerTy(8)) {
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unsigned ProfitableNumElements;
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if (Opcode == Instruction::Store)
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// We use a custom trunc store lowering so v.4b should be profitable.
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ProfitableNumElements = 4;
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else
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// We scalarize the loads because there is not v.4b register and we
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// have to promote the elements to v.2.
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ProfitableNumElements = 8;
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if (cast<FixedVectorType>(Ty)->getNumElements() < ProfitableNumElements) {
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unsigned NumVecElts = cast<FixedVectorType>(Ty)->getNumElements();
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unsigned NumVectorizableInstsToAmortize = NumVecElts * 2;
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// We generate 2 instructions per vector element.
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return NumVectorizableInstsToAmortize * NumVecElts * 2;
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}
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Ty->getScalarSizeInBits() != LT.second.getScalarSizeInBits()) {
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// v4i8 types are lowered to scalar a load/store and sshll/xtn.
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if (VT == MVT::v4i8)
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return 2;
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// Otherwise we need to scalarize.
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return cast<FixedVectorType>(Ty)->getNumElements() * 2;
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}
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return LT.first;
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@ -701,10 +701,10 @@ define i32 @load_extends() #0 {
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi8 = load i8, i8* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi16 = load i16, i16* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi32 = load i32, i32* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %loadv2i8 = load <2 x i8>, <2 x i8>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %loadv4i8 = load <4 x i8>, <4 x i8>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %loadv2i8 = load <2 x i8>, <2 x i8>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv4i8 = load <4 x i8>, <4 x i8>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv8i8 = load <8 x i8>, <8 x i8>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv2i16 = load <2 x i16>, <2 x i16>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %loadv2i16 = load <2 x i16>, <2 x i16>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv4i16 = load <4 x i16>, <4 x i16>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv2i32 = load <2 x i32>, <2 x i32>* undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv4i32 = load <4 x i32>, <4 x i32>* undef
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@ -49,8 +49,8 @@ define void @store8(<8 x i8>* %ptr, <8 x i8> %val) {
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define <4 x i8> @load4(<4 x i8>* %ptr) {
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; CHECK: 'Cost Model Analysis' for function 'load4':
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; CHECK-NEON: Cost Model: Found an estimated cost of 64 for instruction:
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; CHECK-SVE-128: Cost Model: Found an estimated cost of 64 for instruction:
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; CHECK-NEON: Cost Model: Found an estimated cost of 2 for instruction:
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; CHECK-SVE-128: Cost Model: Found an estimated cost of 2 for instruction:
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; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
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; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
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%out = load <4 x i8>, <4 x i8>* %ptr
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@ -59,8 +59,8 @@ define <4 x i8> @load4(<4 x i8>* %ptr) {
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define void @store4(<4 x i8>* %ptr, <4 x i8> %val) {
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; CHECK: 'Cost Model Analysis' for function 'store4':
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; CHECK-NEON: Cost Model: Found an estimated cost of 1 for instruction:
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; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
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; CHECK-NEON: Cost Model: Found an estimated cost of 2 for instruction:
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; CHECK-SVE-128: Cost Model: Found an estimated cost of 2 for instruction:
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; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
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; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
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store <4 x i8> %val, <4 x i8>* %ptr
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@ -23,10 +23,10 @@ define void @getMemoryOpCost() {
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <2 x double> undef, <2 x double>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x float> undef, <4 x float>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x half> undef, <8 x half>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <2 x i8> undef, <2 x i8>* undef, align 2
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i8> undef, <4 x i8>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %1 = load <2 x i8>, <2 x i8>* undef, align 2
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; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %2 = load <4 x i8>, <4 x i8>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x i8> undef, <2 x i8>* undef, align 2
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i8> undef, <4 x i8>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = load <2 x i8>, <2 x i8>* undef, align 2
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = load <4 x i8>, <4 x i8>* undef, align 4
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
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;
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; SIZE-LABEL: 'getMemoryOpCost'
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@ -65,10 +65,10 @@ define void @getMemoryOpCost() {
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: store <2 x double> undef, <2 x double>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: store <4 x float> undef, <4 x float>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: store <8 x half> undef, <8 x half>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <2 x i8> undef, <2 x i8>* undef, align 2
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i8> undef, <4 x i8>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %1 = load <2 x i8>, <2 x i8>* undef, align 2
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %2 = load <4 x i8>, <4 x i8>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <2 x i8> undef, <2 x i8>* undef, align 2
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i8> undef, <4 x i8>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = load <2 x i8>, <2 x i8>* undef, align 2
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = load <4 x i8>, <4 x i8>* undef, align 4
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; SLOW_MISALIGNED_128_STORE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
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;
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store <4 x i64> undef, <4 x i64> * undef
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@ -4,12 +4,11 @@
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; are not profitable.
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; Test with a loop that contains memory accesses of i8 and i32 types. The
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; default maximum VF for NEON is 4, but vectorizing 4 x i8 is not
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; profitable. But we can extend to VF to 8 or 16, at which point the
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; i8 memory accesses become profitable.
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; default maximum VF for NEON is 4. And while we don't have an instruction to
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; load 4 x i8, vectorization might still be profitable.
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define void @test_load_i8_store_i32(i8* noalias %src, i32* noalias %dst, i32 %off, i64 %N) {
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; CHECK-LABEL: @test_load_i8_store_i32(
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; CHECK-NOT: x i8>
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; CHECK: <4 x i8>
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;
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entry:
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br label %loop
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@ -1,20 +1,16 @@
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; REQUIRES: asserts
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; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -S --debug-only=loop-vectorize 2>&1 | FileCheck %s
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; This test shows extremely high interleaving cost that, probably, should be fixed.
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; Due to the high cost, interleaving is not beneficial and the cost model chooses to scalarize
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; the load instructions.
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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%pair = type { i8, i8 }
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; CHECK-LABEL: test
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; CHECK: Found an estimated cost of 20 for VF 2 For instruction: {{.*}} load i8
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; CHECK: Found an estimated cost of 17 for VF 2 For instruction: {{.*}} load i8
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; CHECK: Found an estimated cost of 0 for VF 2 For instruction: {{.*}} load i8
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; CHECK: vector.body
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; CHECK: load i8
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; CHECK: load <4 x i8>
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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define void @test(%pair* %p, i64 %n) {
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@ -171,10 +171,8 @@ define void @PR32038(i32 %n) {
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;
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; MAX-COST-LABEL: @PR32038(
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; MAX-COST-NEXT: entry:
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; MAX-COST-NEXT: [[TMP0:%.*]] = load <2 x i8>, <2 x i8>* bitcast (i8* getelementptr inbounds ([80 x i8], [80 x i8]* @a, i64 0, i64 1) to <2 x i8>*), align 1
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; MAX-COST-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[TMP0]], zeroinitializer
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; MAX-COST-NEXT: [[TMP2:%.*]] = load <2 x i8>, <2 x i8>* bitcast (i8* getelementptr inbounds ([80 x i8], [80 x i8]* @a, i64 0, i64 3) to <2 x i8>*), align 1
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; MAX-COST-NEXT: [[TMP3:%.*]] = icmp eq <2 x i8> [[TMP2]], zeroinitializer
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; MAX-COST-NEXT: [[TMP0:%.*]] = load <4 x i8>, <4 x i8>* bitcast (i8* getelementptr inbounds ([80 x i8], [80 x i8]* @a, i64 0, i64 1) to <4 x i8>*), align 1
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; MAX-COST-NEXT: [[TMP1:%.*]] = icmp eq <4 x i8> [[TMP0]], zeroinitializer
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; MAX-COST-NEXT: [[P8:%.*]] = load i8, i8* getelementptr inbounds ([80 x i8], [80 x i8]* @a, i64 0, i64 5), align 1
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; MAX-COST-NEXT: [[P9:%.*]] = icmp eq i8 [[P8]], 0
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; MAX-COST-NEXT: [[P10:%.*]] = load i8, i8* getelementptr inbounds ([80 x i8], [80 x i8]* @a, i64 0, i64 6), align 2
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@ -186,21 +184,17 @@ define void @PR32038(i32 %n) {
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; MAX-COST-NEXT: br label [[FOR_BODY:%.*]]
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; MAX-COST: for.body:
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; MAX-COST-NEXT: [[P17:%.*]] = phi i32 [ [[P34:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
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; MAX-COST-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1
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; MAX-COST-NEXT: [[TMP5:%.*]] = shufflevector <2 x i1> [[TMP1]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; MAX-COST-NEXT: [[TMP6:%.*]] = shufflevector <4 x i1> poison, <4 x i1> [[TMP5]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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; MAX-COST-NEXT: [[TMP7:%.*]] = shufflevector <2 x i1> [[TMP3]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; MAX-COST-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP6]], <4 x i1> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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; MAX-COST-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP8]], <4 x i32> <i32 -720, i32 -720, i32 -720, i32 -720>, <4 x i32> <i32 -80, i32 -80, i32 -80, i32 -80>
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; MAX-COST-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
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; MAX-COST-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP1]], i32 1
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; MAX-COST-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP1]], i32 0
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; MAX-COST-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i32 3
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; MAX-COST-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -720, i32 -720, i32 -720, i32 -720>, <4 x i32> <i32 -80, i32 -80, i32 -80, i32 -80>
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; MAX-COST-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2
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; MAX-COST-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i32 1
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; MAX-COST-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0
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; MAX-COST-NEXT: [[P27:%.*]] = select i1 [[P9]], i32 -720, i32 -80
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; MAX-COST-NEXT: [[P29:%.*]] = select i1 [[P11]], i32 -720, i32 -80
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; MAX-COST-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP9]])
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; MAX-COST-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[P27]]
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; MAX-COST-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], [[P29]]
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; MAX-COST-NEXT: [[OP_EXTRA:%.*]] = add i32 [[TMP15]], -5
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; MAX-COST-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
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; MAX-COST-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[P27]]
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; MAX-COST-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], [[P29]]
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; MAX-COST-NEXT: [[OP_EXTRA:%.*]] = add i32 [[TMP9]], -5
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; MAX-COST-NEXT: [[P31:%.*]] = select i1 [[P13]], i32 -720, i32 -80
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; MAX-COST-NEXT: [[P32:%.*]] = add i32 [[OP_EXTRA]], [[P31]]
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; MAX-COST-NEXT: [[P33:%.*]] = select i1 [[P15]], i32 -720, i32 -80
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@ -13,52 +13,32 @@ define void @f_noalias(i8* noalias nocapture %dst, i8* noalias nocapture readonl
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[SCALE]], align 16
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; CHECK-NEXT: [[OFFSET:%.*]] = getelementptr inbounds [[STRUCT_WEIGHT_T]], %struct.weight_t* [[W]], i64 0, i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[OFFSET]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = load i8, i8* [[SRC:%.*]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP2]] to i32
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0]], [[CONV]]
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[MUL]], [[TMP1]]
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; CHECK-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp ult i32 [[ADD]], 256
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[ADD]], 0
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; CHECK-NEXT: [[SHR_I:%.*]] = sext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[TOBOOL_NOT_I]], i32 [[ADD]], i32 [[SHR_I]]
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; CHECK-NEXT: [[CONV_I:%.*]] = trunc i32 [[COND_I]] to i8
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; CHECK-NEXT: store i8 [[CONV_I]], i8* [[DST:%.*]], align 1
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 1
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; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[ARRAYIDX_1]], align 1
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; CHECK-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP4]] to i32
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; CHECK-NEXT: [[MUL_1:%.*]] = mul nsw i32 [[TMP0]], [[CONV_1]]
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; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[MUL_1]], [[TMP1]]
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; CHECK-NEXT: [[TOBOOL_NOT_I_1:%.*]] = icmp ult i32 [[ADD_1]], 256
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; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[ADD_1]], 0
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; CHECK-NEXT: [[SHR_I_1:%.*]] = sext i1 [[TMP5]] to i32
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; CHECK-NEXT: [[COND_I_1:%.*]] = select i1 [[TOBOOL_NOT_I_1]], i32 [[ADD_1]], i32 [[SHR_I_1]]
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; CHECK-NEXT: [[CONV_I_1:%.*]] = trunc i32 [[COND_I_1]] to i8
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; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 1
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; CHECK-NEXT: store i8 [[CONV_I_1]], i8* [[ARRAYIDX2_1]], align 1
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 1
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; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i8, i8* [[DST:%.*]], i64 1
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 2
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; CHECK-NEXT: [[TMP6:%.*]] = load i8, i8* [[ARRAYIDX_2]], align 1
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; CHECK-NEXT: [[CONV_2:%.*]] = zext i8 [[TMP6]] to i32
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; CHECK-NEXT: [[MUL_2:%.*]] = mul nsw i32 [[TMP0]], [[CONV_2]]
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; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[MUL_2]], [[TMP1]]
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; CHECK-NEXT: [[TOBOOL_NOT_I_2:%.*]] = icmp ult i32 [[ADD_2]], 256
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; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[ADD_2]], 0
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; CHECK-NEXT: [[SHR_I_2:%.*]] = sext i1 [[TMP7]] to i32
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; CHECK-NEXT: [[COND_I_2:%.*]] = select i1 [[TOBOOL_NOT_I_2]], i32 [[ADD_2]], i32 [[SHR_I_2]]
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; CHECK-NEXT: [[CONV_I_2:%.*]] = trunc i32 [[COND_I_2]] to i8
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; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 2
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; CHECK-NEXT: store i8 [[CONV_I_2]], i8* [[ARRAYIDX2_2]], align 1
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 3
|
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; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[ARRAYIDX_3]], align 1
|
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; CHECK-NEXT: [[CONV_3:%.*]] = zext i8 [[TMP8]] to i32
|
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; CHECK-NEXT: [[MUL_3:%.*]] = mul nsw i32 [[TMP0]], [[CONV_3]]
|
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; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[MUL_3]], [[TMP1]]
|
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; CHECK-NEXT: [[TOBOOL_NOT_I_3:%.*]] = icmp ult i32 [[ADD_3]], 256
|
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; CHECK-NEXT: [[TMP9:%.*]] = icmp sgt i32 [[ADD_3]], 0
|
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; CHECK-NEXT: [[SHR_I_3:%.*]] = sext i1 [[TMP9]] to i32
|
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; CHECK-NEXT: [[COND_I_3:%.*]] = select i1 [[TOBOOL_NOT_I_3]], i32 [[ADD_3]], i32 [[SHR_I_3]]
|
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; CHECK-NEXT: [[CONV_I_3:%.*]] = trunc i32 [[COND_I_3]] to i8
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[SRC]] to <4 x i8>*
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i8>, <4 x i8>* [[TMP2]], align 1
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[TMP3]] to <4 x i32>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP0]], i32 1
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP0]], i32 2
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP0]], i32 3
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <4 x i32> [[TMP8]], [[TMP4]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP1]], i32 1
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP1]], i32 2
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP1]], i32 3
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP9]], [[TMP13]]
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = icmp ult <4 x i32> [[TMP14]], <i32 256, i32 256, i32 256, i32 256>
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = icmp sgt <4 x i32> [[TMP14]], zeroinitializer
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = sext <4 x i1> [[TMP16]] to <4 x i32>
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> [[TMP14]], <4 x i32> [[TMP17]]
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = trunc <4 x i32> [[TMP18]] to <4 x i8>
|
||||
; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 3
|
||||
; CHECK-NEXT: store i8 [[CONV_I_3]], i8* [[ARRAYIDX2_3]], align 1
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = bitcast i8* [[DST]] to <4 x i8>*
|
||||
; CHECK-NEXT: store <4 x i8> [[TMP19]], <4 x i8>* [[TMP20]], align 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
|
|
|
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Loading…
Reference in New Issue