forked from OSchip/llvm-project
AMDGPU/GlobalISel: Add some missing tests for extract selection
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@ -199,6 +199,45 @@ body: |
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...
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---
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name: extract_sgpr_s32_from_v3s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2
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; CHECK-LABEL: name: extract_sgpr_s32_from_v3s32
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; CHECK: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
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; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub2
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; CHECK: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]]
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%0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
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%1:sgpr(s32) = G_EXTRACT %0, 0
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%2:sgpr(s32) = G_EXTRACT %0, 32
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%3:sgpr(s32) = G_EXTRACT %0, 64
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S_ENDPGM 0, implicit %0, implicit %2, implicit %3
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...
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---
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name: extract_sgpr_v2s32_from_v3s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2
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; CHECK-LABEL: name: extract_sgpr_v2s32_from_v3s32
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; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub0_sub1 = COPY $sgpr0_sgpr1_sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[COPY]].sub0_sub1
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; CHECK: S_ENDPGM 0, implicit [[COPY1]]
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%0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
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%1:sgpr(<2 x s32>) = G_EXTRACT %0, 0
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S_ENDPGM 0, implicit %1
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...
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---
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name: extract_sgpr_v3s32_from_v4s32
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legalized: true
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