forked from OSchip/llvm-project
[AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above
Adding usage of VSSRC and VSFRC when adding the live in registers on AIX. This matches the behaviour of the rest of PPC Subtargets. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D104396
This commit is contained in:
Zarko Todorovski
parent
6de42e104f
commit
ee6ca9c7df
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@ -6738,8 +6738,11 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
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return true;
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return true;
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}
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}
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// So far, this function is only used by LowerFormalArguments_AIX()
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static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
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static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
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bool IsPPC64) {
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bool IsPPC64,
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bool HasP8Vector,
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bool HasVSX) {
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assert((IsPPC64 || SVT != MVT::i64) &&
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assert((IsPPC64 || SVT != MVT::i64) &&
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"i64 should have been split for 32-bit codegen.");
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"i64 should have been split for 32-bit codegen.");
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@ -6751,9 +6754,9 @@ static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
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case MVT::i64:
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case MVT::i64:
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return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
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return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
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case MVT::f32:
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case MVT::f32:
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return &PPC::F4RCRegClass;
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return HasP8Vector ? &PPC::VSSRCRegClass : &PPC::F4RCRegClass;
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case MVT::f64:
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case MVT::f64:
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return &PPC::F8RCRegClass;
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return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass;
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case MVT::v4f32:
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case MVT::v4f32:
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case MVT::v4i32:
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case MVT::v4i32:
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case MVT::v8i16:
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case MVT::v8i16:
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@ -6929,7 +6932,9 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
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assert(VA.getValNo() == OriginalValNo &&
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assert(VA.getValNo() == OriginalValNo &&
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"ValNo mismatch between custom MemLoc and RegLoc.");
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"ValNo mismatch between custom MemLoc and RegLoc.");
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MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy;
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MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy;
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MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
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MF.addLiveIn(VA.getLocReg(),
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getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
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Subtarget.hasVSX()));
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};
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};
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HandleMemLoc();
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HandleMemLoc();
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@ -7068,8 +7073,10 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
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if (VA.isRegLoc() && !VA.needsCustom()) {
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if (VA.isRegLoc() && !VA.needsCustom()) {
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MVT::SimpleValueType SVT = ValVT.SimpleTy;
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MVT::SimpleValueType SVT = ValVT.SimpleTy;
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unsigned VReg =
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Register VReg =
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MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
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MF.addLiveIn(VA.getLocReg(),
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getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
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Subtarget.hasVSX()));
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
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if (ValVT.isScalarInteger() &&
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if (ValVT.isScalarInteger() &&
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(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
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(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
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@ -0,0 +1,115 @@
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
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; RUN: -verify-machineinstrs -stop-after=finalize-isel < %s | \
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; RUN: FileCheck --check-prefixes=POWR8,VSX %s
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
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; RUN: -verify-machineinstrs -mattr=-vsx -stop-after=finalize-isel \
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; RUN: < %s | FileCheck %s --check-prefixes=NOVSX,NOP8V
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
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; RUN: -verify-machineinstrs -mattr=vsx -stop-after=finalize-isel \
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; RUN: < %s | FileCheck %s --check-prefixes=VSX,NOP8V
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define float @vssr(float %a, float %b, float %c, float %d, float %e) {
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entry:
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%add = fadd float %a, %b
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%add1 = fadd float %add, %c
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%add2 = fadd float %add1, %d
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%add3 = fadd float %add2, %e
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ret float %add3
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}
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; POWR8-LABEL: name: vssr
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; POWR8: - { id: 0, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 1, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 2, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 3, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 4, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 5, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 6, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 7, class: vssrc, preferred-register: '' }
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; POWR8: - { id: 8, class: vssrc, preferred-register: '' }
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; POWR8: %4:vssrc = COPY $f5
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; POWR8: %3:vssrc = COPY $f4
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; POWR8: %2:vssrc = COPY $f3
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; POWR8: %1:vssrc = COPY $f2
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; POWR8: %0:vssrc = COPY $f1
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; POWR8: %5:vssrc = nofpexcept XSADDSP %0, %1
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; POWR8: %6:vssrc = nofpexcept XSADDSP killed %5, %2
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; POWR8: %7:vssrc = nofpexcept XSADDSP killed %6, %3
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; POWR8: %8:vssrc = nofpexcept XSADDSP killed %7, %4
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; POWR8: $f1 = COPY %8
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; NOP8V-LABEL: name: vssr
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; NOP8V: registers:
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; NOP8V: - { id: 0, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 1, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 2, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 3, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 4, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 5, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 6, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 7, class: f4rc, preferred-register: '' }
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; NOP8V: - { id: 8, class: f4rc, preferred-register: '' }
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; NOP8V: %4:f4rc = COPY $f5
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; NOP8V: %3:f4rc = COPY $f4
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; NOP8V: %2:f4rc = COPY $f3
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; NOP8V: %1:f4rc = COPY $f2
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; NOP8V: %0:f4rc = COPY $f1
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; NOP8V: %5:f4rc = nofpexcept FADDS %0, %1, implicit $rm
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; NOP8V: %6:f4rc = nofpexcept FADDS killed %5, %2, implicit $rm
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; NOP8V: %7:f4rc = nofpexcept FADDS killed %6, %3, implicit $rm
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; NOP8V: %8:f4rc = nofpexcept FADDS killed %7, %4, implicit $rm
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; NOP8V: $f1 = COPY %8
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define double @vsfr(double %a, double %b, double %c, double %d, double %e) {
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entry:
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%add = fadd double %a, %b
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%add1 = fadd double %add, %c
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%add2 = fadd double %add1, %d
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%add3 = fadd double %add2, %e
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ret double %add3
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}
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; VSX-LABEL: vsfr
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; VSX: registers:
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; VSX: - { id: 0, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 1, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 2, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 3, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 4, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 5, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 6, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 7, class: vsfrc, preferred-register: '' }
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; VSX: - { id: 8, class: vsfrc, preferred-register: '' }
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; VSX: %4:vsfrc = COPY $f5
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; VSX: %3:vsfrc = COPY $f4
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; VSX: %2:vsfrc = COPY $f3
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; VSX: %1:vsfrc = COPY $f2
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; VSX: %0:vsfrc = COPY $f1
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; VSX: %5:vsfrc = nofpexcept XSADDDP %0, %1, implicit $rm
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; VSX: %6:vsfrc = nofpexcept XSADDDP killed %5, %2, implicit $rm
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; VSX: %7:vsfrc = nofpexcept XSADDDP killed %6, %3, implicit $rm
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; VSX: %8:vsfrc = nofpexcept XSADDDP killed %7, %4, implicit $rm
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; VSX: $f1 = COPY %8
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; NOVSX-LABEL: vsfr
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; NOVSX: registers:
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; NOVSX: - { id: 0, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 1, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 2, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 3, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 4, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 5, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 6, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 7, class: f8rc, preferred-register: '' }
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; NOVSX: - { id: 8, class: f8rc, preferred-register: '' }
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; NOVSX: %4:f8rc = COPY $f5
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; NOVSX: %3:f8rc = COPY $f4
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; NOVSX: %2:f8rc = COPY $f3
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; NOVSX: %1:f8rc = COPY $f2
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; NOVSX: %0:f8rc = COPY $f1
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; NOVSX: %5:f8rc = nofpexcept FADD %0, %1, implicit $rm
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; NOVSX: %6:f8rc = nofpexcept FADD killed %5, %2, implicit $rm
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; NOVSX: %7:f8rc = nofpexcept FADD killed %6, %3, implicit $rm
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; NOVSX: %8:f8rc = nofpexcept FADD killed %7, %4, implicit $rm
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; NOVSX: $f1 = COPY %8
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