forked from OSchip/llvm-project
Revert "Intel(R) Memory Protection Extensions (Intel(R) MPX) support."
This reverts commit rL280668 because the register tests fail on i386
Linux.
I investigated a little bit what causes the failure - there are missing
registers when running 'register read -a'.
This is the output I got at the bottom:
"""
...
Memory Protection Extensions:
bnd0 = {0x0000000000000000 0x0000000000000000}
bnd1 = {0x0000000000000000 0x0000000000000000}
bnd2 = {0x0000000000000000 0x0000000000000000}
bnd3 = {0x0000000000000000 0x0000000000000000}
unknown:
2 registers were unavailable.
"""
Also looking at the packets exchanged between the client and server:
"""
...
history[308] tid=0x7338 < 19> send packet: $qRegisterInfo4a#d7
history[309] tid=0x7338 < 130> read packet:
$name:bnd0;bitsize:128;offset:1032;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:101;dwarf:101;#48
history[310] tid=0x7338 < 19> send packet: $qRegisterInfo4b#d8
history[311] tid=0x7338 < 130> read packet:
$name:bnd1;bitsize:128;offset:1048;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:102;dwarf:102;#52
history[312] tid=0x7338 < 19> send packet: $qRegisterInfo4c#d9
history[313] tid=0x7338 < 130> read packet:
$name:bnd2;bitsize:128;offset:1064;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:103;dwarf:103;#53
history[314] tid=0x7338 < 19> send packet: $qRegisterInfo4d#da
history[315] tid=0x7338 < 130> read packet:
$name:bnd3;bitsize:128;offset:1080;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:104;dwarf:104;#54
history[316] tid=0x7338 < 19> send packet: $qRegisterInfo4e#db
history[317] tid=0x7338 < 76> read packet:
$name:bndcfgu;bitsize:64;offset:1096;encoding:vector;format:vector-uint8;#99
history[318] tid=0x7338 < 19> send packet: $qRegisterInfo4f#dc
history[319] tid=0x7338 < 78> read packet:
$name:bndstatus;bitsize:64;offset:1104;encoding:vector;format:vector-uint8;#8e
...
"""
The bndcfgu and bndstatus registers don't have the 'Memory Protections
Extension' set. I looked at the code and it seems that that is set
correctly.
So I'm not sure what's the problem or where does it come from.
Also there is a second failure related to something like this in the
tests:
"""
registerSet.GetName().lower()
"""
For some reason the registerSet.GetName() returns None.
llvm-svn: 280703
This commit is contained in:
Dimitar Vlahovski
parent
209b6e2e78
commit
ee44a92df6
|
|
@ -1,4 +1,4 @@
|
|||
LEVEL = ../../../make
|
||||
LEVEL = ../../make
|
||||
|
||||
CXX_SOURCES := main.cpp a.cpp
|
||||
|
||||
|
|
@ -41,12 +41,11 @@ class RegisterCommandsTestCase(TestBase):
|
|||
if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
|
||||
self.runCmd("register read xmm0")
|
||||
self.runCmd("register read ymm15") # may be available
|
||||
self.runCmd("register read bnd0") # may be available
|
||||
elif self.getArchitecture() in ['arm']:
|
||||
self.runCmd("register read s0")
|
||||
self.runCmd("register read q15") # may be available
|
||||
|
||||
self.expect("register read -s 4", substrs = ['invalid register set index: 4'], error = True)
|
||||
self.expect("register read -s 3", substrs = ['invalid register set index: 3'], error = True)
|
||||
|
||||
@skipIfiOSSimulator
|
||||
@skipIfTargetAndroid(archs=["i386"]) # Writing of mxcsr register fails, presumably due to a kernel/hardware problem
|
||||
|
|
@ -290,14 +289,12 @@ class RegisterCommandsTestCase(TestBase):
|
|||
self.runCmd("register write " + st0regname + " \"{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}\"")
|
||||
self.expect("register read " + st0regname + " --format f", substrs = [st0regname + ' = 0'])
|
||||
|
||||
has_avx = False
|
||||
has_mpx = False
|
||||
has_avx = False
|
||||
registerSets = currentFrame.GetRegisters() # Returns an SBValueList.
|
||||
for registerSet in registerSets:
|
||||
if 'advanced vector extensions' in registerSet.GetName().lower():
|
||||
has_avx = True
|
||||
if 'memory protection extension' in registerSet.GetName().lower():
|
||||
has_mpx = True
|
||||
break
|
||||
|
||||
if has_avx:
|
||||
new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0c 0x0d 0x0e 0x0f}"
|
||||
|
|
@ -307,21 +304,6 @@ class RegisterCommandsTestCase(TestBase):
|
|||
else:
|
||||
self.runCmd("register read ymm0")
|
||||
|
||||
if has_mpx:
|
||||
# Test write and read for bnd0.
|
||||
new_value_w = "{0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10}"
|
||||
self.runCmd("register write bnd0 \'" + new_value_w + "\'")
|
||||
new_value_r = "{0x0807060504030201 0x100f0e0d0c0b0a09}"
|
||||
self.expect("register read bnd0", substrs = ['bnd0 = ', new_value_r])
|
||||
self.expect("expr $bnd0", substrs = ['vector_type'])
|
||||
|
||||
# Test write and for bndstatus.
|
||||
new_value = "{0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08}"
|
||||
self.write_and_read(currentFrame, "bndstatus", new_value)
|
||||
self.expect("expr $bndstatus", substrs = ['vector_type'])
|
||||
else:
|
||||
self.runCmd("register read bnd0")
|
||||
|
||||
def convenience_registers(self):
|
||||
"""Test convenience registers."""
|
||||
self.common_setup()
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
LEVEL = ../../../make
|
||||
|
||||
CXX_SOURCES := main.cpp
|
||||
CXXFLAGS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd
|
||||
LDFLAGS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd
|
||||
include $(LEVEL)/Makefile.rules
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
"""
|
||||
Test the MPX registers.
|
||||
"""
|
||||
|
||||
from __future__ import print_function
|
||||
|
||||
import os, sys, time
|
||||
import re
|
||||
import lldb
|
||||
from lldbsuite.test.decorators import *
|
||||
from lldbsuite.test.lldbtest import *
|
||||
from lldbsuite.test import lldbutil
|
||||
|
||||
|
||||
class RegisterCommandsTestCase(TestBase):
|
||||
|
||||
mydir = TestBase.compute_mydir(__file__)
|
||||
|
||||
def setUp(self):
|
||||
TestBase.setUp(self)
|
||||
self.has_teardown = False
|
||||
|
||||
def tearDown(self):
|
||||
self.dbg.GetSelectedTarget().GetProcess().Destroy()
|
||||
TestBase.tearDown(self)
|
||||
|
||||
@skipIfiOSSimulator
|
||||
@skipIf(compiler="clang")
|
||||
@expectedFailureAll(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"])
|
||||
@skipIf(archs=no_match(['amd64', 'i386', 'x86_64']))
|
||||
def test_mpx_registers_with_example_code(self):
|
||||
"""Test MPX registers with example code."""
|
||||
self.build()
|
||||
self.mpx_registers_with_example_code()
|
||||
|
||||
def mpx_registers_with_example_code(self):
|
||||
"""Test MPX registers after running example code."""
|
||||
self.line = line_number('main.cpp', '// Set a break point here.')
|
||||
|
||||
exe = os.path.join(os.getcwd(), "a.out")
|
||||
self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
|
||||
|
||||
self.runCmd('settings set target.inline-breakpoint-strategy always')
|
||||
self.addTearDownHook(
|
||||
lambda: self.runCmd("settings set target.inline-breakpoint-strategy always"))
|
||||
|
||||
lldbutil.run_break_set_by_file_and_line(self, "main.cpp", self.line, num_expected_locations=1)
|
||||
self.runCmd("run", RUN_SUCCEEDED)
|
||||
|
||||
self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
|
||||
substrs = ["stop reason = breakpoint 1."])
|
||||
|
||||
self.expect("register read -s 3",
|
||||
substrs = ['bnd0 = {0x0000000000000010 0xffffffffffffffe6}',
|
||||
'bnd1 = {0x0000000000000020 0xffffffffffffffd6}',
|
||||
'bnd2 = {0x0000000000000030 0xffffffffffffffc6}',
|
||||
'bnd3 = {0x0000000000000040 0xffffffffffffffb6}',
|
||||
'bndcfgu = {0x01 0x80 0xb5 0x76 0xff 0x7f 0x00 0x00}',
|
||||
'bndstatus = {0x02 0x80 0xb5 0x76 0xff 0x7f 0x00 0x00}'])
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
//===-- main.cpp ------------------------------------------------*- C++ -*-===//
|
||||
////
|
||||
//// The LLVM Compiler Infrastructure
|
||||
////
|
||||
//// This file is distributed under the University of Illinois Open Source
|
||||
//// License. See LICENSE.TXT for details.
|
||||
////
|
||||
////===----------------------------------------------------------------------===//
|
||||
//
|
||||
|
||||
#include <cpuid.h>
|
||||
#include <cstddef>
|
||||
|
||||
int
|
||||
main(int argc, char const *argv[])
|
||||
{
|
||||
unsigned int rax, rbx, rcx, rdx;
|
||||
|
||||
// Check if XSAVE is enabled.
|
||||
if (!__get_cpuid(1, &rax, &rbx, &rcx, &rdx) || (rcx & bit_OSXSAVE) != bit_OSXSAVE)
|
||||
return -1;
|
||||
|
||||
// Check if MPX is enabled.
|
||||
if (__get_cpuid_max(0, NULL) > 7)
|
||||
{
|
||||
__cpuid_count(7, 0, rax, rbx, rcx, rdx);
|
||||
if ((rbx & bit_MPX) != bit_MPX)
|
||||
return -1;
|
||||
}
|
||||
else
|
||||
return -1;
|
||||
|
||||
// Run MPX test code.
|
||||
#if defined(__x86_64__)
|
||||
asm("mov $16, %rax\n\t"
|
||||
"mov $9, %rdx\n\t"
|
||||
"bndmk (%rax,%rdx), %bnd0\n\t"
|
||||
"mov $32, %rax\n\t"
|
||||
"mov $9, %rdx\n\t"
|
||||
"bndmk (%rax,%rdx), %bnd1\n\t"
|
||||
"mov $48, %rax\n\t"
|
||||
"mov $9, %rdx\n\t"
|
||||
"bndmk (%rax,%rdx), %bnd2\n\t"
|
||||
"mov $64, %rax\n\t"
|
||||
"mov $9, %rdx\n\t"
|
||||
"bndmk (%rax,%rdx), %bnd3\n\t"
|
||||
"bndstx %bnd3, (%rax) \n\t"
|
||||
"nop\n\t");
|
||||
#endif
|
||||
#if defined(__i386__)
|
||||
asm("mov $16, %eax\n\t"
|
||||
"mov $9, %edx\n\t"
|
||||
"bndmk (%eax,%edx), %bnd0\n\t"
|
||||
"mov $32, %eax\n\t"
|
||||
"mov $9, %edx\n\t"
|
||||
"bndmk (%eax,%edx), %bnd1\n\t"
|
||||
"mov $48, %eax\n\t"
|
||||
"mov $9, %edx\n\t"
|
||||
"bndmk (%eax,%edx), %bnd2\n\t"
|
||||
"mov $64, %eax\n\t"
|
||||
"mov $9, %edx\n\t"
|
||||
"bndmk (%eax,%edx), %bnd3\n\t"
|
||||
"bndstx %bnd3, (%eax)\n\t"
|
||||
"nop\n\t");
|
||||
#endif
|
||||
asm("nop\n\t"); // Set a break point here.
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -104,12 +104,7 @@ enum dwarf_regnums
|
|||
dwarf_mm4,
|
||||
dwarf_mm5,
|
||||
dwarf_mm6,
|
||||
dwarf_mm7,
|
||||
|
||||
dwarf_bnd0 = 101,
|
||||
dwarf_bnd1,
|
||||
dwarf_bnd2,
|
||||
dwarf_bnd3
|
||||
dwarf_mm7
|
||||
};
|
||||
|
||||
static RegisterInfo g_register_infos[] =
|
||||
|
|
@ -164,13 +159,7 @@ static RegisterInfo g_register_infos[] =
|
|||
{ "ymm4" , nullptr, 32, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , dwarf_ymm4 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "ymm5" , nullptr, 32, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , dwarf_ymm5 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "ymm6" , nullptr, 32, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , dwarf_ymm6 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "ymm7" , nullptr, 32, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , dwarf_ymm7 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "bnd0" , nullptr, 16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd0 , dwarf_bnd0 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "bnd1" , nullptr, 16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd1 , dwarf_bnd1 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "bnd2" , nullptr, 16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd2 , dwarf_bnd2 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "bnd3" , nullptr, 16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd3 , dwarf_bnd3 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "bndcfgu", nullptr, 8, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0},
|
||||
{ "bndstatus", nullptr, 8, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0}
|
||||
{ "ymm7" , nullptr, 32, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , dwarf_ymm7 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0}
|
||||
};
|
||||
|
||||
static const uint32_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
|
||||
|
|
|
|||
|
|
@ -95,11 +95,7 @@ enum dwarf_regnums
|
|||
dwarf_ymm12,
|
||||
dwarf_ymm13,
|
||||
dwarf_ymm14,
|
||||
dwarf_ymm15,
|
||||
dwarf_bnd0 = 126,
|
||||
dwarf_bnd1,
|
||||
dwarf_bnd2,
|
||||
dwarf_bnd3
|
||||
dwarf_ymm15
|
||||
};
|
||||
|
||||
static RegisterInfo g_register_infos[] =
|
||||
|
|
@ -178,13 +174,7 @@ static RegisterInfo g_register_infos[] =
|
|||
{ "ymm12" , nullptr,32, 0, eEncodingVector, eFormatVectorOfUInt8, { dwarf_ymm12 , dwarf_ymm12 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "ymm13" , nullptr,32, 0, eEncodingVector, eFormatVectorOfUInt8, { dwarf_ymm13 , dwarf_ymm13 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "ymm14" , nullptr,32, 0, eEncodingVector, eFormatVectorOfUInt8, { dwarf_ymm14 , dwarf_ymm14 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "ymm15" , nullptr,32, 0, eEncodingVector, eFormatVectorOfUInt8, { dwarf_ymm15 , dwarf_ymm15 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "bnd0" , nullptr,16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd0 , dwarf_bnd0 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "bnd1" , nullptr,16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd1 , dwarf_bnd1 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "bnd2" , nullptr,16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd2 , dwarf_bnd2 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "bnd3" , nullptr,16, 0, eEncodingVector, eFormatVectorOfUInt64,{ dwarf_bnd3 , dwarf_bnd3 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "bndcfgu", nullptr,8, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 },
|
||||
{ "bndstatus", nullptr,8, 0, eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 }
|
||||
{ "ymm15" , nullptr,32, 0, eEncodingVector, eFormatVectorOfUInt8, { dwarf_ymm15 , dwarf_ymm15 , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM }, nullptr, nullptr, nullptr, 0 }
|
||||
};
|
||||
|
||||
static const uint32_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
|
||||
|
|
|
|||
|
|
@ -130,21 +130,6 @@ namespace
|
|||
static_assert((sizeof(g_avx_regnums_i386) / sizeof(g_avx_regnums_i386[0])) - 1 == k_num_avx_registers_i386,
|
||||
" g_avx_regnums_i386 has wrong number of register infos");
|
||||
|
||||
// x64 32-bit MPX registers.
|
||||
static const uint32_t
|
||||
g_mpx_regnums_i386[] =
|
||||
{
|
||||
lldb_bnd0_i386,
|
||||
lldb_bnd1_i386,
|
||||
lldb_bnd2_i386,
|
||||
lldb_bnd3_i386,
|
||||
lldb_bndcfgu_i386,
|
||||
lldb_bndstatus_i386,
|
||||
LLDB_INVALID_REGNUM // register sets need to end with this flag
|
||||
};
|
||||
static_assert((sizeof(g_mpx_regnums_i386) / sizeof(g_mpx_regnums_i386[0])) - 1 == k_num_mpx_registers_i386,
|
||||
"g_mpx_regnums_x86_64 has wrong number of register infos");
|
||||
|
||||
// x86 64-bit general purpose registers.
|
||||
static const
|
||||
uint32_t g_gpr_regnums_x86_64[] =
|
||||
|
|
@ -306,47 +291,29 @@ namespace
|
|||
static_assert((sizeof(g_avx_regnums_x86_64) / sizeof(g_avx_regnums_x86_64[0])) - 1 == k_num_avx_registers_x86_64,
|
||||
"g_avx_regnums_x86_64 has wrong number of register infos");
|
||||
|
||||
// x86 64-bit MPX registers.
|
||||
static const uint32_t
|
||||
g_mpx_regnums_x86_64[] =
|
||||
{
|
||||
lldb_bnd0_x86_64,
|
||||
lldb_bnd1_x86_64,
|
||||
lldb_bnd2_x86_64,
|
||||
lldb_bnd3_x86_64,
|
||||
lldb_bndcfgu_x86_64,
|
||||
lldb_bndstatus_x86_64,
|
||||
LLDB_INVALID_REGNUM // register sets need to end with this flag
|
||||
};
|
||||
static_assert((sizeof(g_mpx_regnums_x86_64) / sizeof(g_mpx_regnums_x86_64[0])) - 1 == k_num_mpx_registers_x86_64,
|
||||
"g_mpx_regnums_x86_64 has wrong number of register infos");
|
||||
|
||||
// Number of register sets provided by this context.
|
||||
enum
|
||||
{
|
||||
k_num_extended_register_sets = 1,
|
||||
k_num_register_sets = 4
|
||||
k_num_register_sets = 3
|
||||
};
|
||||
|
||||
// Register sets for x86 32-bit.
|
||||
static const RegisterSet
|
||||
g_reg_sets_i386[k_num_register_sets] =
|
||||
{
|
||||
{ "General Purpose Registers", "gpr", k_num_gpr_registers_i386, g_gpr_regnums_i386 },
|
||||
{ "Floating Point Registers", "fpu", k_num_fpr_registers_i386, g_fpu_regnums_i386 },
|
||||
{ "Advanced Vector Extensions", "avx", k_num_avx_registers_i386, g_avx_regnums_i386 },
|
||||
{ "Memory Protection Extensions", "mpx", k_num_mpx_registers_i386, g_mpx_regnums_i386 }
|
||||
{ "General Purpose Registers", "gpr", k_num_gpr_registers_i386, g_gpr_regnums_i386 },
|
||||
{ "Floating Point Registers", "fpu", k_num_fpr_registers_i386, g_fpu_regnums_i386 },
|
||||
{ "Advanced Vector Extensions", "avx", k_num_avx_registers_i386, g_avx_regnums_i386 }
|
||||
};
|
||||
|
||||
// Register sets for x86 64-bit.
|
||||
static const RegisterSet
|
||||
g_reg_sets_x86_64[k_num_register_sets] =
|
||||
{
|
||||
{ "General Purpose Registers", "gpr", k_num_gpr_registers_x86_64, g_gpr_regnums_x86_64 },
|
||||
{ "Floating Point Registers", "fpu", k_num_fpr_registers_x86_64, g_fpu_regnums_x86_64 },
|
||||
{ "Advanced Vector Extensions", "avx", k_num_avx_registers_x86_64, g_avx_regnums_x86_64 },
|
||||
{ "Memory Protection Extensions", "mpx", k_num_mpx_registers_x86_64, g_mpx_regnums_x86_64 }
|
||||
|
||||
{ "General Purpose Registers", "gpr", k_num_gpr_registers_x86_64, g_gpr_regnums_x86_64 },
|
||||
{ "Floating Point Registers", "fpu", k_num_fpr_registers_x86_64, g_fpu_regnums_x86_64 },
|
||||
{ "Advanced Vector Extensions", "avx", k_num_avx_registers_x86_64, g_avx_regnums_x86_64 }
|
||||
};
|
||||
}
|
||||
|
||||
|
|
@ -401,7 +368,6 @@ NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64 (const Arch
|
|||
m_fpr (),
|
||||
m_iovec (),
|
||||
m_ymm_set (),
|
||||
m_mpx_set (),
|
||||
m_reg_info (),
|
||||
m_gpr_x86_64 ()
|
||||
{
|
||||
|
|
@ -413,7 +379,6 @@ NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64 (const Arch
|
|||
m_reg_info.num_gpr_registers = k_num_gpr_registers_i386;
|
||||
m_reg_info.num_fpr_registers = k_num_fpr_registers_i386;
|
||||
m_reg_info.num_avx_registers = k_num_avx_registers_i386;
|
||||
m_reg_info.num_mpx_registers = k_num_mpx_registers_i386;
|
||||
m_reg_info.last_gpr = k_last_gpr_i386;
|
||||
m_reg_info.first_fpr = k_first_fpr_i386;
|
||||
m_reg_info.last_fpr = k_last_fpr_i386;
|
||||
|
|
@ -425,10 +390,6 @@ NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64 (const Arch
|
|||
m_reg_info.last_xmm = lldb_xmm7_i386;
|
||||
m_reg_info.first_ymm = lldb_ymm0_i386;
|
||||
m_reg_info.last_ymm = lldb_ymm7_i386;
|
||||
m_reg_info.first_mpxr = lldb_bnd0_i386;
|
||||
m_reg_info.last_mpxr = lldb_bnd3_i386;
|
||||
m_reg_info.first_mpxc = lldb_bndcfgu_i386;
|
||||
m_reg_info.last_mpxc = lldb_bndstatus_i386;
|
||||
m_reg_info.first_dr = lldb_dr0_i386;
|
||||
m_reg_info.gpr_flags = lldb_eflags_i386;
|
||||
break;
|
||||
|
|
@ -437,7 +398,6 @@ NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64 (const Arch
|
|||
m_reg_info.num_gpr_registers = k_num_gpr_registers_x86_64;
|
||||
m_reg_info.num_fpr_registers = k_num_fpr_registers_x86_64;
|
||||
m_reg_info.num_avx_registers = k_num_avx_registers_x86_64;
|
||||
m_reg_info.num_mpx_registers = k_num_mpx_registers_x86_64;
|
||||
m_reg_info.last_gpr = k_last_gpr_x86_64;
|
||||
m_reg_info.first_fpr = k_first_fpr_x86_64;
|
||||
m_reg_info.last_fpr = k_last_fpr_x86_64;
|
||||
|
|
@ -449,10 +409,6 @@ NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64 (const Arch
|
|||
m_reg_info.last_xmm = lldb_xmm15_x86_64;
|
||||
m_reg_info.first_ymm = lldb_ymm0_x86_64;
|
||||
m_reg_info.last_ymm = lldb_ymm15_x86_64;
|
||||
m_reg_info.first_mpxr = lldb_bnd0_x86_64;
|
||||
m_reg_info.last_mpxr = lldb_bnd3_x86_64;
|
||||
m_reg_info.first_mpxc = lldb_bndcfgu_x86_64;
|
||||
m_reg_info.last_mpxc = lldb_bndstatus_x86_64;
|
||||
m_reg_info.first_dr = lldb_dr0_x86_64;
|
||||
m_reg_info.gpr_flags = lldb_rflags_x86_64;
|
||||
break;
|
||||
|
|
@ -598,28 +554,7 @@ NativeRegisterContextLinux_x86_64::ReadRegister (const RegisterInfo *reg_info, R
|
|||
return error;
|
||||
}
|
||||
}
|
||||
if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr)
|
||||
{
|
||||
if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoMPX(reg))
|
||||
reg_value.SetBytes(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes, reg_info->byte_size,
|
||||
byte_order);
|
||||
else
|
||||
{
|
||||
error.SetErrorString("failed to copy mpx register value");
|
||||
return error;
|
||||
}
|
||||
}
|
||||
if (reg >= m_reg_info.first_mpxc && reg <= m_reg_info.last_mpxc)
|
||||
{
|
||||
if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoMPX(reg))
|
||||
reg_value.SetBytes(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes, reg_info->byte_size,
|
||||
byte_order);
|
||||
else
|
||||
{
|
||||
error.SetErrorString("failed to copy mpx register value");
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
if (reg_value.GetType() != RegisterValue::eTypeBytes)
|
||||
error.SetErrorString ("write failed - type was expected to be RegisterValue::eTypeBytes");
|
||||
|
||||
|
|
@ -699,26 +634,6 @@ NativeRegisterContextLinux_x86_64::WriteRegister (const RegisterInfo *reg_info,
|
|||
if (!CopyYMMtoXSTATE(reg_index, GetByteOrder()))
|
||||
return Error ("CopyYMMtoXSTATE() failed");
|
||||
}
|
||||
if (reg_index >= m_reg_info.first_mpxr && reg_index <= m_reg_info.last_mpxr)
|
||||
{
|
||||
if (GetFPRType() != eFPRTypeXSAVE)
|
||||
return Error("target processor does not support MPX");
|
||||
|
||||
::memcpy(m_mpx_set.mpxr[reg_index - m_reg_info.first_mpxr].bytes, reg_value.GetBytes(),
|
||||
reg_value.GetByteSize());
|
||||
if (!CopyMPXtoXSTATE(reg_index))
|
||||
return Error("CopyMPXtoXSTATE() failed");
|
||||
}
|
||||
if (reg_index >= m_reg_info.first_mpxc && reg_index <= m_reg_info.last_mpxc)
|
||||
{
|
||||
if (GetFPRType() != eFPRTypeXSAVE)
|
||||
return Error("target processor does not support MPX");
|
||||
|
||||
::memcpy(m_mpx_set.mpxc[reg_index - m_reg_info.first_mpxc].bytes, reg_value.GetBytes(),
|
||||
reg_value.GetByteSize());
|
||||
if (!CopyMPXtoXSTATE(reg_index))
|
||||
return Error("CopyMPXtoXSTATE() failed");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -762,12 +677,6 @@ NativeRegisterContextLinux_x86_64::WriteRegister (const RegisterInfo *reg_info,
|
|||
if (!CopyYMMtoXSTATE(reg_index, GetByteOrder()))
|
||||
return Error ("CopyYMMtoXSTATE() failed");
|
||||
}
|
||||
|
||||
if (IsMPX(reg_index))
|
||||
{
|
||||
if (!CopyMPXtoXSTATE(reg_index))
|
||||
return Error("CopyMPXtoXSTATE() failed");
|
||||
}
|
||||
return Error ();
|
||||
}
|
||||
return Error ("failed - register wasn't recognized to be a GPR or an FPR, write strategy unknown");
|
||||
|
|
@ -818,17 +727,6 @@ NativeRegisterContextLinux_x86_64::ReadAllRegisterValues (lldb::DataBufferSP &da
|
|||
}
|
||||
}
|
||||
|
||||
for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc; ++reg)
|
||||
{
|
||||
if (!CopyXSTATEtoMPX(reg))
|
||||
{
|
||||
error.SetErrorStringWithFormat(
|
||||
"NativeRegisterContextLinux_x86_64::%s CopyXSTATEtoMPX() failed for reg num %" PRIu32, __FUNCTION__,
|
||||
reg);
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Copy the extended register state including the assembled ymm registers.
|
||||
::memcpy (dst, &m_fpr, sizeof (m_fpr));
|
||||
}
|
||||
|
|
@ -908,17 +806,6 @@ NativeRegisterContextLinux_x86_64::WriteAllRegisterValues (const lldb::DataBuffe
|
|||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc; ++reg)
|
||||
{
|
||||
if (!CopyMPXtoXSTATE(reg))
|
||||
{
|
||||
error.SetErrorStringWithFormat(
|
||||
"NativeRegisterContextLinux_x86_64::%s CopyMPXtoXSTATE() failed for reg num %" PRIu32, __FUNCTION__,
|
||||
reg);
|
||||
return error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return error;
|
||||
|
|
@ -933,7 +820,7 @@ NativeRegisterContextLinux_x86_64::IsRegisterSetAvailable (uint32_t set_index) c
|
|||
if (GetFPRType () == eFPRTypeXSAVE)
|
||||
{
|
||||
// AVX is the first extended register set.
|
||||
num_sets += 2;
|
||||
++num_sets;
|
||||
}
|
||||
return (set_index < num_sets);
|
||||
}
|
||||
|
|
@ -983,8 +870,7 @@ NativeRegisterContextLinux_x86_64::IsFPR(uint32_t reg_index, FPRType fpr_type) c
|
|||
bool generic_fpr = IsFPR(reg_index);
|
||||
|
||||
if (fpr_type == eFPRTypeXSAVE)
|
||||
return generic_fpr || IsAVX(reg_index) || IsMPX(reg_index);
|
||||
|
||||
return generic_fpr || IsAVX(reg_index);
|
||||
return generic_fpr;
|
||||
}
|
||||
|
||||
|
|
@ -1119,7 +1005,6 @@ NativeRegisterContextLinux_x86_64::ReadFPR ()
|
|||
{
|
||||
const FPRType fpr_type = GetFPRType ();
|
||||
const lldb_private::ArchSpec& target_arch = GetRegisterInfoInterface().GetTargetArchitecture();
|
||||
|
||||
switch (fpr_type)
|
||||
{
|
||||
case FPRType::eFPRTypeFXSAVE:
|
||||
|
|
@ -1144,50 +1029,6 @@ NativeRegisterContextLinux_x86_64::ReadFPR ()
|
|||
}
|
||||
}
|
||||
|
||||
bool
|
||||
NativeRegisterContextLinux_x86_64::IsMPX(uint32_t reg_index) const
|
||||
{
|
||||
return (m_reg_info.first_mpxr <= reg_index && reg_index <= m_reg_info.last_mpxc);
|
||||
}
|
||||
|
||||
bool
|
||||
NativeRegisterContextLinux_x86_64::CopyXSTATEtoMPX(uint32_t reg)
|
||||
{
|
||||
if (!IsMPX(reg))
|
||||
return false;
|
||||
|
||||
if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr)
|
||||
{
|
||||
::memcpy(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes,
|
||||
m_fpr.xstate.xsave.mpxr[reg - m_reg_info.first_mpxr].bytes, sizeof(MPXReg));
|
||||
}
|
||||
else
|
||||
{
|
||||
::memcpy(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes,
|
||||
m_fpr.xstate.xsave.mpxc[reg - m_reg_info.first_mpxc].bytes, sizeof(MPXCsr));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
NativeRegisterContextLinux_x86_64::CopyMPXtoXSTATE(uint32_t reg)
|
||||
{
|
||||
if (!IsMPX(reg))
|
||||
return false;
|
||||
|
||||
if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr)
|
||||
{
|
||||
::memcpy(m_fpr.xstate.xsave.mpxr[reg - m_reg_info.first_mpxr].bytes,
|
||||
m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes, sizeof(MPXReg));
|
||||
}
|
||||
else
|
||||
{
|
||||
::memcpy(m_fpr.xstate.xsave.mpxc[reg - m_reg_info.first_mpxc].bytes,
|
||||
m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes, sizeof(MPXCsr));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
Error
|
||||
NativeRegisterContextLinux_x86_64::IsWatchpointHit(uint32_t wp_index, bool &is_hit)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -111,7 +111,6 @@ namespace process_linux {
|
|||
uint32_t num_gpr_registers;
|
||||
uint32_t num_fpr_registers;
|
||||
uint32_t num_avx_registers;
|
||||
uint32_t num_mpx_registers;
|
||||
|
||||
uint32_t last_gpr;
|
||||
uint32_t first_fpr;
|
||||
|
|
@ -125,10 +124,6 @@ namespace process_linux {
|
|||
uint32_t last_xmm;
|
||||
uint32_t first_ymm;
|
||||
uint32_t last_ymm;
|
||||
uint32_t first_mpxr;
|
||||
uint32_t last_mpxr;
|
||||
uint32_t first_mpxc;
|
||||
uint32_t last_mpxc;
|
||||
|
||||
uint32_t first_dr;
|
||||
uint32_t gpr_flags;
|
||||
|
|
@ -139,7 +134,6 @@ namespace process_linux {
|
|||
FPR m_fpr;
|
||||
IOVEC m_iovec;
|
||||
YMM m_ymm_set;
|
||||
MPX m_mpx_set;
|
||||
RegInfo m_reg_info;
|
||||
uint64_t m_gpr_x86_64[k_num_gpr_registers_x86_64];
|
||||
uint32_t m_fctrl_offset_in_userarea;
|
||||
|
|
@ -166,16 +160,7 @@ namespace process_linux {
|
|||
CopyYMMtoXSTATE(uint32_t reg, lldb::ByteOrder byte_order);
|
||||
|
||||
bool
|
||||
CopyXSTATEtoMPX(uint32_t reg);
|
||||
|
||||
bool
|
||||
CopyMPXtoXSTATE(uint32_t reg);
|
||||
|
||||
bool
|
||||
IsAVX(uint32_t reg_index) const;
|
||||
|
||||
bool
|
||||
IsMPX(uint32_t reg_index) const;
|
||||
IsAVX (uint32_t reg_index) const;
|
||||
};
|
||||
|
||||
} // namespace process_linux
|
||||
|
|
|
|||
|
|
@ -116,13 +116,10 @@ enum
|
|||
dwarf_ss_i386 = 42,
|
||||
dwarf_ds_i386 = 43,
|
||||
dwarf_fs_i386 = 44,
|
||||
dwarf_gs_i386 = 45,
|
||||
dwarf_gs_i386 = 45
|
||||
|
||||
// I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
|
||||
// then differentiate based on size of the register.
|
||||
dwarf_bnd0_i386 = 101,
|
||||
dwarf_bnd1_i386,
|
||||
dwarf_bnd2_i386,
|
||||
dwarf_bnd3_i386,
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
|
|
@ -219,11 +216,6 @@ enum
|
|||
dwarf_ymm13h_x86_64,
|
||||
dwarf_ymm14h_x86_64,
|
||||
dwarf_ymm15h_x86_64,
|
||||
// MPX registers
|
||||
dwarf_bnd0_x86_64 = 126,
|
||||
dwarf_bnd1_x86_64,
|
||||
dwarf_bnd2_x86_64,
|
||||
dwarf_bnd3_x86_64,
|
||||
// AVX2 Vector Mask Registers
|
||||
// dwarf_k0_x86_64 = 118,
|
||||
// dwarf_k1_x86_64,
|
||||
|
|
@ -299,39 +291,19 @@ struct YMM
|
|||
YMMReg ymm[16]; // assembled from ymmh and xmm registers
|
||||
};
|
||||
|
||||
struct MPXReg
|
||||
{
|
||||
uint8_t bytes[16]; // MPX 128 bit bound registers
|
||||
};
|
||||
|
||||
struct MPXCsr
|
||||
{
|
||||
uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively BNDCSR state)
|
||||
};
|
||||
|
||||
struct MPX
|
||||
{
|
||||
MPXReg mpxr[4];
|
||||
MPXCsr mpxc[2];
|
||||
};
|
||||
|
||||
struct XSAVE_HDR
|
||||
{
|
||||
uint64_t xstate_bv; // OS enabled xstate mask to determine the extended states supported by the processor
|
||||
uint64_t xcomp_bv; // Mask to indicate the format of the XSAVE area and of the XRSTOR instruction
|
||||
uint64_t reserved1[1];
|
||||
uint64_t reserved1[2];
|
||||
uint64_t reserved2[5];
|
||||
} __attribute__((packed));
|
||||
|
||||
// x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
|
||||
struct XSAVE
|
||||
// x86 extensions to FXSAVE (i.e. for AVX processors)
|
||||
struct XSAVE
|
||||
{
|
||||
FXSAVE i387; // floating point registers typical in i387_fxsave_struct
|
||||
XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the following extensions are usable
|
||||
YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes are in FXSAVE.xmm for compatibility with SSE)
|
||||
uint64_t reserved3[16];
|
||||
MPXReg mpxr[4]; // MPX BNDREG state, containing 128-bit bound registers BND0-BND3
|
||||
MPXCsr mpxc[2]; // MPX BNDCSR state, containing 64-bit BNDCFGU and BNDSTATUS registers
|
||||
// Slot any extensions to the register file here
|
||||
} __attribute__((packed, aligned (64)));
|
||||
|
||||
|
|
|
|||
|
|
@ -35,16 +35,6 @@
|
|||
LLVM_EXTENSION offsetof(FXSAVE, xmm[7]) + \
|
||||
sizeof(XMMReg) + (32 * reg_index))
|
||||
|
||||
#define BNDR_OFFSET(reg_index) \
|
||||
(LLVM_EXTENSION offsetof(UserArea, i387) + \
|
||||
LLVM_EXTENSION offsetof(FPR, xstate) + \
|
||||
LLVM_EXTENSION offsetof(XSAVE, mpxr[reg_index]))
|
||||
|
||||
#define BNDC_OFFSET(reg_index) \
|
||||
(LLVM_EXTENSION offsetof(UserArea, i387) + \
|
||||
LLVM_EXTENSION offsetof(FPR, xstate) + \
|
||||
LLVM_EXTENSION offsetof(XSAVE, mpxc[reg_index]))
|
||||
|
||||
// Number of bytes needed to represent a FPR.
|
||||
#if !defined(FPR_SIZE)
|
||||
#define FPR_SIZE(reg) sizeof(((FXSAVE*)NULL)->reg)
|
||||
|
|
@ -59,10 +49,6 @@
|
|||
// Number of bytes needed to represent a YMM register.
|
||||
#define YMM_SIZE sizeof(YMMReg)
|
||||
|
||||
// Number of bytes needed to represent MPX registers.
|
||||
#define BNDR_SIZE sizeof(MPXReg)
|
||||
#define BNDC_SIZE sizeof(MPXCsr)
|
||||
|
||||
// Note that the size and offset will be updated by platform-specific classes.
|
||||
#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
|
||||
{ #reg, alt, sizeof(((GPR*)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, \
|
||||
|
|
@ -99,18 +85,6 @@
|
|||
{ LLDB_INVALID_REGNUM, dwarf_xmm##i##_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg##i##_i386 }, \
|
||||
NULL, NULL, NULL, 0}
|
||||
|
||||
#define DEFINE_BNDR(reg, i) \
|
||||
{ #reg#i, NULL, BNDR_SIZE, LLVM_EXTENSION BNDR_OFFSET(i), \
|
||||
eEncodingVector, eFormatVectorOfUInt64, \
|
||||
{ dwarf_##reg##i##_i386, dwarf_##reg##i##_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg##i##_i386 }, \
|
||||
NULL, NULL }
|
||||
|
||||
#define DEFINE_BNDC(name, i) \
|
||||
{ #name, NULL, BNDC_SIZE, LLVM_EXTENSION BNDC_OFFSET(i), \
|
||||
eEncodingVector, eFormatVectorOfUInt8, \
|
||||
{ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##name##_x86_64 }, \
|
||||
NULL, NULL }
|
||||
|
||||
#define DEFINE_DR(reg, i) \
|
||||
{ #reg#i, NULL, DR_SIZE, DR_OFFSET(i), eEncodingUint, eFormatHex, \
|
||||
{ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
|
||||
|
|
@ -214,15 +188,6 @@ g_register_infos_i386[] =
|
|||
DEFINE_YMM(ymm, 6),
|
||||
DEFINE_YMM(ymm, 7),
|
||||
|
||||
// MPX registers
|
||||
DEFINE_BNDR(bnd, 0),
|
||||
DEFINE_BNDR(bnd, 1),
|
||||
DEFINE_BNDR(bnd, 2),
|
||||
DEFINE_BNDR(bnd, 3),
|
||||
|
||||
DEFINE_BNDC(bndcfgu, 0),
|
||||
DEFINE_BNDC(bndstatus, 1),
|
||||
|
||||
// Debug registers for lldb internal use
|
||||
DEFINE_DR(dr, 0),
|
||||
DEFINE_DR(dr, 1),
|
||||
|
|
|
|||
|
|
@ -34,16 +34,6 @@
|
|||
LLVM_EXTENSION offsetof(XSAVE, ymmh[0]) + \
|
||||
(32 * reg_index))
|
||||
|
||||
#define BNDR_OFFSET(reg_index) \
|
||||
(LLVM_EXTENSION offsetof(UserArea, fpr) + \
|
||||
LLVM_EXTENSION offsetof(FPR, xstate) + \
|
||||
LLVM_EXTENSION offsetof(XSAVE, mpxr[reg_index]))
|
||||
|
||||
#define BNDC_OFFSET(reg_index) \
|
||||
(LLVM_EXTENSION offsetof(UserArea, fpr) + \
|
||||
LLVM_EXTENSION offsetof(FPR, xstate) + \
|
||||
LLVM_EXTENSION offsetof(XSAVE, mpxc[reg_index]))
|
||||
|
||||
#ifdef DECLARE_REGISTER_INFOS_X86_64_STRUCT
|
||||
|
||||
// Number of bytes needed to represent a FPR.
|
||||
|
|
@ -58,10 +48,6 @@
|
|||
// Number of bytes needed to represent a YMM register.
|
||||
#define YMM_SIZE sizeof(YMMReg)
|
||||
|
||||
// Number of bytes needed to represent MPX registers.
|
||||
#define BNDR_SIZE sizeof(MPXReg)
|
||||
#define BNDC_SIZE sizeof(MPXCsr)
|
||||
|
||||
#define DR_SIZE sizeof(((DBG*)NULL)->dr[0])
|
||||
|
||||
// RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB
|
||||
|
|
@ -99,18 +85,6 @@
|
|||
{ dwarf_##reg##i##h_x86_64, dwarf_##reg##i##h_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg##i##_x86_64 }, \
|
||||
NULL, NULL, NULL, 0}
|
||||
|
||||
#define DEFINE_BNDR(reg, i) \
|
||||
{ #reg#i, NULL, BNDR_SIZE, LLVM_EXTENSION BNDR_OFFSET(i), \
|
||||
eEncodingVector, eFormatVectorOfUInt64, \
|
||||
{ dwarf_##reg##i##_x86_64, dwarf_##reg##i##_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##reg##i##_x86_64 }, \
|
||||
NULL, NULL }
|
||||
|
||||
#define DEFINE_BNDC(name, i) \
|
||||
{ #name, NULL, BNDC_SIZE, LLVM_EXTENSION BNDC_OFFSET(i), \
|
||||
eEncodingVector, eFormatVectorOfUInt8, \
|
||||
{ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, lldb_##name##_x86_64 }, \
|
||||
NULL, NULL }
|
||||
|
||||
#define DEFINE_DR(reg, i) \
|
||||
{ #reg#i, NULL, DR_SIZE, DR_OFFSET(i), eEncodingUint, eFormatHex, \
|
||||
{ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
|
||||
|
|
@ -277,15 +251,6 @@ g_register_infos_x86_64[] =
|
|||
DEFINE_YMM(ymm, 14),
|
||||
DEFINE_YMM(ymm, 15),
|
||||
|
||||
// MPX registers
|
||||
DEFINE_BNDR(bnd, 0),
|
||||
DEFINE_BNDR(bnd, 1),
|
||||
DEFINE_BNDR(bnd, 2),
|
||||
DEFINE_BNDR(bnd, 3),
|
||||
|
||||
DEFINE_BNDC(bndcfgu, 0),
|
||||
DEFINE_BNDC(bndstatus, 1),
|
||||
|
||||
// Debug registers for lldb internal use
|
||||
DEFINE_DR(dr, 0),
|
||||
DEFINE_DR(dr, 1),
|
||||
|
|
|
|||
|
|
@ -106,18 +106,6 @@ namespace lldb_private
|
|||
lldb_ymm7_i386,
|
||||
k_last_avx_i386 = lldb_ymm7_i386,
|
||||
|
||||
k_first_mpxr_i386,
|
||||
lldb_bnd0_i386 = k_first_mpxr_i386,
|
||||
lldb_bnd1_i386,
|
||||
lldb_bnd2_i386,
|
||||
lldb_bnd3_i386,
|
||||
k_last_mpxr = lldb_bnd3_i386,
|
||||
|
||||
k_first_mpxc_i386,
|
||||
lldb_bndcfgu_i386 = k_first_mpxc_i386,
|
||||
lldb_bndstatus_i386,
|
||||
k_last_mpxc_i386 = lldb_bndstatus_i386,
|
||||
|
||||
lldb_dr0_i386,
|
||||
lldb_dr1_i386,
|
||||
lldb_dr2_i386,
|
||||
|
|
@ -131,8 +119,7 @@ namespace lldb_private
|
|||
k_num_gpr_registers_i386 = k_last_gpr_i386 - k_first_gpr_i386 + 1,
|
||||
k_num_fpr_registers_i386 = k_last_fpr_i386 - k_first_fpr_i386 + 1,
|
||||
k_num_avx_registers_i386 = k_last_avx_i386 - k_first_avx_i386 + 1,
|
||||
k_num_mpx_registers_i386 = k_last_mpxc_i386 - k_first_mpxr_i386 + 1,
|
||||
k_num_user_registers_i386 = k_num_gpr_registers_i386 + k_num_fpr_registers_i386 + k_num_avx_registers_i386 + k_num_mpx_registers_i386,
|
||||
k_num_user_registers_i386 = k_num_gpr_registers_i386 + k_num_fpr_registers_i386 + k_num_avx_registers_i386,
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
|
|
@ -287,18 +274,6 @@ namespace lldb_private
|
|||
lldb_ymm15_x86_64,
|
||||
k_last_avx_x86_64 = lldb_ymm15_x86_64,
|
||||
|
||||
k_first_mpxr_x86_64,
|
||||
lldb_bnd0_x86_64 = k_first_mpxr_x86_64,
|
||||
lldb_bnd1_x86_64,
|
||||
lldb_bnd2_x86_64,
|
||||
lldb_bnd3_x86_64,
|
||||
k_last_mpxr_x86_64 = lldb_bnd3_x86_64,
|
||||
|
||||
k_first_mpxc_x86_64,
|
||||
lldb_bndcfgu_x86_64 = k_first_mpxc_x86_64,
|
||||
lldb_bndstatus_x86_64,
|
||||
k_last_mpxc_x86_64 = lldb_bndstatus_x86_64,
|
||||
|
||||
lldb_dr0_x86_64,
|
||||
lldb_dr1_x86_64,
|
||||
lldb_dr2_x86_64,
|
||||
|
|
@ -312,8 +287,7 @@ namespace lldb_private
|
|||
k_num_gpr_registers_x86_64 = k_last_gpr_x86_64 - k_first_gpr_x86_64 + 1,
|
||||
k_num_fpr_registers_x86_64 = k_last_fpr_x86_64 - k_first_fpr_x86_64 + 1,
|
||||
k_num_avx_registers_x86_64 = k_last_avx_x86_64 - k_first_avx_x86_64 + 1,
|
||||
k_num_mpx_registers_x86_64 = k_last_mpxc_x86_64 - k_first_mpxr_x86_64 + 1,
|
||||
k_num_user_registers_x86_64 = k_num_gpr_registers_x86_64 + k_num_fpr_registers_x86_64 + k_num_avx_registers_x86_64 + k_num_mpx_registers_x86_64,
|
||||
k_num_user_registers_x86_64 = k_num_gpr_registers_x86_64 + k_num_fpr_registers_x86_64 + k_num_avx_registers_x86_64,
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1566,7 +1566,6 @@ GDBRemoteCommunicationServerLLGS::Handle_qRegisterInfo (StringExtractorGDBRemote
|
|||
case eFormatVectorOfSInt32: response.PutCString ("format:vector-sint32;"); break;
|
||||
case eFormatVectorOfUInt32: response.PutCString ("format:vector-uint32;"); break;
|
||||
case eFormatVectorOfFloat32: response.PutCString ("format:vector-float32;"); break;
|
||||
case eFormatVectorOfUInt64: response.PutCString ("format:vector-uint64;"); break;
|
||||
case eFormatVectorOfUInt128: response.PutCString ("format:vector-uint128;"); break;
|
||||
default: break;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -610,7 +610,6 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
|
|||
.Case("vector-sint32", eFormatVectorOfSInt32)
|
||||
.Case("vector-uint32", eFormatVectorOfUInt32)
|
||||
.Case("vector-float32", eFormatVectorOfFloat32)
|
||||
.Case("vector-uint64", eFormatVectorOfUInt64)
|
||||
.Case("vector-uint128", eFormatVectorOfUInt128)
|
||||
.Default(eFormatInvalid);
|
||||
}
|
||||
|
|
@ -4546,8 +4545,6 @@ ParseRegisters (XMLNode feature_node, GdbServerTargetInfo &target_info, GDBRemot
|
|||
reg_info.format = eFormatVectorOfUInt32;
|
||||
else if (value == "vector-float32")
|
||||
reg_info.format = eFormatVectorOfFloat32;
|
||||
else if (value == "vector-uint64")
|
||||
reg_info.format = eFormatVectorOfUInt64;
|
||||
else if (value == "vector-uint128")
|
||||
reg_info.format = eFormatVectorOfUInt128;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue