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Tidy up. 80 column. 

llvm-svn: 144538
This commit is contained in:
Jim Grosbach 2011-11-14 17:52:47 +00:00
parent 0ffbcc959d
commit ee201faeac
1 changed files with 8 additions and 5 deletions
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11
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -714,7 +714,7 @@ public:
bool isBitfield() const { return Kind == k_BitfieldDescriptor; } bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
bool isPostIdxReg() const { bool isPostIdxReg() const {
return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
} }
bool isMemNoOffset(bool alignOK = false) const { bool isMemNoOffset(bool alignOK = false) const {
if (!isMemory()) if (!isMemory())
@ -1101,7 +1101,8 @@ public:
void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!"); assert(N == 3 && "Invalid number of operands!");
assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); assert(isRegShiftedReg() &&
"addRegShiftedRegOperands() on non RegShiftedReg!");
Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
Inst.addOperand(MCOperand::CreateImm( Inst.addOperand(MCOperand::CreateImm(
@ -1110,7 +1111,8 @@ public:
void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 2 && "Invalid number of operands!");
assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); assert(isRegShiftedImm() &&
"addRegShiftedImmOperands() on non RegShiftedImm!");
Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
Inst.addOperand(MCOperand::CreateImm( Inst.addOperand(MCOperand::CreateImm(
ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
@ -1426,7 +1428,8 @@ public:
void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!"); assert(N == 3 && "Invalid number of operands!");
unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, unsigned Val =
ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
Memory.ShiftImm, Memory.ShiftType); Memory.ShiftImm, Memory.ShiftType);
Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));