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[SelectionDAG] Add support for vector demandedelts in MUL opcodes 

llvm-svn: 286471
This commit is contained in:
Simon Pilgrim 2016-11-10 16:27:42 +00:00
parent bb2338e939
commit ee187fd6e7
2 changed files with 7 additions and 11 deletions
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8
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2166,11 +2166,13 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
break; break;
} }
case ISD::MUL: { case ISD::MUL: {
computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts,
computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); Depth + 1);
computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
Depth + 1);
// If low bits are zero in either operand, output low known-0 bits. // If low bits are zero in either operand, output low known-0 bits.
// Also compute a conserative estimate for high known-0 bits. // Also compute a conservative estimate for high known-0 bits.
// More trickiness is possible, but this is sufficient for the // More trickiness is possible, but this is sufficient for the
// interesting case of alignment computation. // interesting case of alignment computation.
KnownOne.clearAllBits(); KnownOne.clearAllBits();

10
llvm/test/CodeGen/X86/known-bits-vector.ll
View File

@ -173,18 +173,12 @@ define <4 x i32> @knownbits_mask_ashr_shuffle_lshr(<4 x i32> %a0) nounwind {
define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; X32-LABEL: knownbits_mask_mul_shuffle_shl: ; X32-LABEL: knownbits_mask_mul_shuffle_shl:
; X32: # BB#0: ; X32: # BB#0:
; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: vpmulld %xmm0, %xmm1, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vpslld $22, %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_mul_shuffle_shl: ; X64-LABEL: knownbits_mask_mul_shuffle_shl:
; X64: # BB#0: ; X64: # BB#0:
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: vpmulld %xmm0, %xmm1, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X64-NEXT: vpslld $22, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536> %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
%2 = mul <4 x i32> %a1, %1 %2 = mul <4 x i32> %a1, %1