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[InstCombine][X86] Show failure to simplify demanded vector elts for x86 per-element vector shifts

This commit is contained in:
Simon Pilgrim 2022-04-28 15:00:38 +01:00
parent b809c4cdb7
commit ee157b207b
2 changed files with 28 additions and 0 deletions
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14
llvm/test/Transforms/InstCombine/X86/x86-avx2-inseltpoison.ll
View File

@ -106,5 +106,19 @@ define <8 x float> @elts_test_vpermps(<8 x float> %a0, <8 x i32> %a1) {
ret <8 x float> %3
}
define <4 x i32> @elts_test_vpsrlvd(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @elts_test_vpsrlvd(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[A1:%.*]], i32 0, i64 3
; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[A0:%.*]], <4 x i32> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
;
%1 = insertelement <4 x i32> %a1, i32 0, i64 3
%2 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %1)
%3 = shufflevector <4 x i32> %2, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %3
}
declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>)
declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>)
declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>)

14
llvm/test/Transforms/InstCombine/X86/x86-avx2.ll
View File

@ -106,5 +106,19 @@ define <8 x float> @elts_test_vpermps(<8 x float> %a0, <8 x i32> %a1) {
ret <8 x float> %3
}
define <4 x i32> @elts_test_vpsrlvd(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @elts_test_vpsrlvd(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[A1:%.*]], i32 0, i64 3
; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[A0:%.*]], <4 x i32> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
;
%1 = insertelement <4 x i32> %a1, i32 0, i64 3
%2 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %1)
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %3
}
declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>)
declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>)
declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>)